driver cell in one domain and receiver in another voltage domain timing closure

Driver cell in one domain and receiver in another

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driver cell in one domain and receiver in another voltage domain timing closure problems and excessive crowbar switching currents Level shifters are not critically required for a step-down change (high to low) but still better to have them If specialized high-to-low level shifter cells were NOT provided in the library then the entire library would have to be re-characterized to allow accurate static timing analysis Overhead of level shifters can be mitigated by doing conversions at register boundaries and embedding the level shifting inside the flip-flop Chapter 7: Power Analysis and Optimization 7-46
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Effective level shifter should be designed at transistor level Level shifters are mostly designed to shift only one direction - either from a higher voltage to a lower one or converse Design interfaces that can operate in both directions may appear attractive from a system perspective but requires non-standard implementation components and tooling Synthesis tools such as Power Compiler and IC Compiler can identify and insert level-shifter cells Ex : A gate-level model buffer-type of a L-to-H level shifter cell(Buffer_Type_LH_Level_shifter){ is_level_shifter:true; level_shifter_type:LH ; pg_pin(VDDL){voltage_name:VDDL; pg_type:primary_power; std_cell_main_rail:true;} ... V DDL V DDH V SS V DDL Domain V DDH Domain Chapter 7: Power Analysis and Optimization 7-47
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Level Shifter for High to Low (not necessary) H2L level shifters can be just two inverters in series. Require only one voltage supply from destination (low) domain Only introduces buffer delay its impact on timing is small Additional buffers use high voltage placed in high domain If the distance is long, additional buffers outside of the high voltage domain are needed , which leads to complex voltage routing Level shifter Chapter 7: Power Analysis and Optimization 7-48
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Level Shifter for Low to High (necessary) There are several design techniques. Below is a simple one This design takes a buffered and an inverted form of the lower voltage signal and uses this to drive a cross-coupled transistor structure running at the higher voltage Similarly to H2L, the L2H level shifter is placed at the destination domain (which is in high voltage domain for this case) Since both high & low voltages are needed , routing is complex Additional buffers use low voltage placed in low domain If the distance is long (and library does not have strong buffers), additional buffers outside of the low voltage domain are needed, which leads to complex voltage routing Chapter 7: Power Analysis and Optimization 7-49
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Example : Dual-Supply Inside a Logic Block Path starts with V DDH is switched to V DDL (gray logic gates) when slack is positive (extra delay available) Level shifting is done in the flip-flops at the end of the paths So minimum energy consumption is achieved when all logic paths have the same delay (by any mean) H2L not critical L2H LS’s are in FF’s Chapter 7: Power Analysis and Optimization 7-50
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