# Func2 func1 func0 aluop2 func2 func1 func0 aluctr1

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Unformatted text preview: func<2> & func<1> & !func<0> ALUop<2> & !func<2> & func<1> & !func<0> • ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0> ALUop<2> & !func<2> & !func<0> • ALUctr<0> = !ALUop<2> & ALUop<1> + ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & ALUop<2> & !func<3> & func<2> & ! ! func<1> & func<0> + ALUop<2> & func<1> & func<0> + ALUop<2> & func<3> func<3> & !func<2> & func<1> & & !func<2> & func<1> & !func<0> !func<0> 28 28 Logic for each control Logic for each control signal signal • nPC_sel nPC_sel <= if ((OP == BEQ) && <= if ((OP == BEQ) && (EQUAL)) then “Br” else “+4” (EQUAL)) then “Br” else “+4” • ALUsrc ALUsrc <= <= if (OP == “Rtype”) then if (OP == “Rtype”) then “regB” else “immed” “regB” else “immed” • ALUctr ALUctr <= if (OP == “Rtype”) then <= if (OP == “Rtype”) then funct funct elseif (OP == ORi) then “OR” elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” elseif (OP == BEQ) then “sub” else “add” else “add” 29 29 Step 5: Logic for each control Step 5: Logic for each control signal signal (cont.) (cont.) • ExtOp ExtOp <= <= _____________ _____________ • MemWr MemWr <= <= _____________ _____________ • MemtoReg MemtoReg <= <= _____________ _____________ • RegWr: RegWr: <= <= _____________ _____________ • RegDst: RegDst: <= <= _____________ _____________ 30 30 Logic for each control Logic for each control signal signal • ExtOp ExtOp <= if (OP == ORi) then “zero” else <= if (OP == ORi) then “zero” else “sign” “sign” • MemWr MemWr <= (OP == Store) <= (OP == Store) • MemtoReg MemtoReg <= (OP == Load) <= (OP == Load) • RegWr: RegWr: <= if ((OP == Store) || (OP == <= if ((OP == Store) || (OP == BEQ) BEQ) || (OP == JUMP || (OP == JUMP ) ) ) then 0 else 1 ) then 0 else 1 • RegDst: RegDst: <= if ((OP == Load) || (OP == <= if ((OP == Load) || (OP == ORi)) then 0 else 1 ORi)) then 0 else 1 31 31 The “Truth Table” for the Main Control The “Truth Table” for the Main Control R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPC_sel Jump ExtOp ALUop (Symbolic) 1 1 x “R-type” 1 1 Or 1 1 1 1 Add x 1 x 1 1 Add x x 1 x Subtract x x x 1 x xxx op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 ALUop <2> 1 x ALUop <1> 1 x ALUop <0> 1 x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc : 32 32 The “Truth Table” for RegWrite The “Truth Table” for RegWrite R-type ori lw sw beq...
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• Fall '05
• WeiChungHsu
• Trigraph, Rw Ra Rb, Datapath Inst Memory, 32-bit Registers busB

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