Chapter 03 - Digital Logic

Logical completeness byu csecen 124 chapter 3 digital

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Logical Completeness
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 33 Storage Elements Everything so far has been combinational logic the output is strictly a function of the current inputs Computing systems need storage elements for holding previously computed values for saving state Two types of locks: Sequential Logic 4 1 8 4 Combinational – Success depends only on the values , not the order in which they are set. 30 15 5 10 20 25 Sequential - Success depends on the sequence of values (e.g, R-13, L-22, R-3).
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 34 Bi-Stability = Key to Memory When there are 2 stable states - a bi-stable circuit RS Latch Sequential Logic 0 1 1 This is also a stable state – it will sit like this forever 1 0 0 This is a stable state – it will sit like this forever q q s r q q s r 1 1 0 1 1 1 1 0
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 35 RS Latch – Bi-Stable Circuit Sequential Logic 0 1 1 0 1 0 0 1 1 1 0 1 q q s r 1 1 1 0 This is also a stable state – it will sit like this forever q q s r This is a stable state – it will sit like this forever 1 0 1 1 1 1 0 1 1 1 1 0
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 36 Gated D Latch Output q gets value from input d only when we is high we stands for write enable , think of it as a load signal s r q q d we LATCH Symbol WE D Q D-Latch Symbols are abstractions! Latch
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 37 Register A computer register is a place to store a collection of bits Very fast memory Numbered right to left (LSB on the right) D-Latch d0 q0 D-Latch d1 q1 D-Latch d2 q2 D-Latch d3 q3 we REGISTER Symbol Register d q we Latch
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 38 Memory A collection of addressable locations Address selects which location to read from or write to Memory address q n we d m m A memory with n address wires has 2 n locations. The number of data wires in equal the number of data wires out. Memory is changed with we is asserted. q always reflects the contents stored at the addressed memory location. Memory can be viewed as a large collection of slower registers. Memory
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 39 Building a Memory From Latches 2-to-4 Decoder a1 a0 00 01 10 11 Register Register Register Register we we we we writeEnable d input q output This is a functional view. The key parts are: address decoder memory cells (registers) output selector (mux) Memory address q n we d m m MEMORY Symbol n = 2 address q 0 q 1 q 2 q 3 Memory
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 40 A 12-Bit Memory 4 words, each 3 bits wide Word line “00” Word line “01” Word line “10” Word line “11” Latch Only one word line is high at any given time. Memory
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BYU CS/ECEn 124 Chapter 3 - Digital Logic 41 Reading a 12-Bit Memory Each column forms a sort of multiplexor Only one of the AND gates in the column will be enabled. Thus, they allow one row out of 4 to be selected for reading.
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  • Fall '08
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  • Logic gate, Finite State Machine, BYU CS/ECEn

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