Dspic33epic24e program memory ds70000613 in the

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“dsPIC33E/PIC24E Program Memory” (DS70000613) in the “dsPIC33/ PIC24 Family Reference Manual” . On dsPIC33EV devices, overhead-free circular buffers (Modulo Addressing) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. The X AGU Circular Addressing can be used with any of the MCU class of instructions. The X AGU also supports Bit-Reversed Addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms. Figure 3-1 illustrates the block diagram of the dsPIC33EVXXXGM00X/10X family devices. 3.4 Addressing Modes The CPU supports these addressing modes: Inherent (no operand) • Relative • Literal Memory Direct Register Direct Register Indirect Each instruction is associated with a predefined addressing mode group, depending upon its functional requirements. As many as six addressing modes are supported for each instruction. Note 1: This data sheet summarizes the features of the dsPIC33EVXXXGM00X/10X family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “CPU” (DS70359) in the “dsPIC33/PIC24 Family Reference Manual ”, which is available from the Microchip web site ( ). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information.
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dsPIC33EVXXXGM00X/10X FAMILY DS70005144E-page 22 2013-2016 Microchip Technology Inc. FIGURE 3-1: dsPIC33EVXXXGM00X/10X FAMILY CPU BLOCK DIAGRAM 16 PCH 16 Program Counter 16-Bit ALU 24 24 24 24 X Data Bus PCU 16 16 16 Divide Support Engine DSP ROM Latch 16 Y Data Bus EA MUX X RAGU X WAGU Y AGU 16 24 16 16 16 16 16 16 16 8 Interrupt Controller PSV and Table Data Access Control Block Stack Control Logic Loop Control Logic Data Latch Data Latch Y Data RAM X Data RAM Address Latch Address Latch 16 Data Latch 16 16 16 X Address Bus Y Address Bus 24 Literal Data Program Memory Address Latch Power, Reset and Oscillator Control Signals to Various Blocks Ports Peripheral Modules Modules PCL 16 x 16 W Register Array IR Instruction Decode and Control
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2013-2016 Microchip Technology Inc. DS70005144E-page 23 dsPIC33EVXXXGM00X/10X FAMILY 3.5 Programmer’s Model The programmer’s model for the dsPIC33EVXXXGM00X/ 10X family is shown in Figure 3-2 . All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 3-1 lists a description of each register. In addition to the registers contained in the programmer’s model, the dsPIC33EVXXXGM00X/10X family devices contain control registers for Modulo Addressing and Bit- Reversed Addressing, and interrupts. These registers are described in subsequent sections of this document.
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