# Implemented using two instructions for example addi

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implemented using two instructions. For example: addi \$at, \$t1, 104 # add the offset to a temporary lw \$t0, \$at # new way of doing lw \$t0, 104(\$t1) What changes would you make to the single-cycle datapath and control if this simplified architecture were to be used? 2) Architecture and Performance Assume that the logic blocks needed to implement a single- cycle processor’s datapath have the following latencies:
I-Mem Add Mux ALU Regs D-Mem Sign-extend sll 2 P1 400ps 100ps 30ps 120ps 200ps 350ps 20ps 0ps P2 500ps 150ps 100ps 180ps 220ps 1000ps 90ps 20ps (a) Which of the two sets of latencies (P1 or P2) seem more reasonable to you? Why? (b) What is the clock cycle time for P1 and P2 if the only type of instructions we need to support are ALU instructions ( add , and , etc.)? (c) What is the clock cycle time for P1 and P2 if we only had to support lw instructions? (d) What is the clock cycle time for P1 and P2 if we must support add , beq , lw , and instructions? 3) Fault Tolerance When silicon chips are fabricated, defects in materials and manufacturing errors can result in defective circuits. A very common defect is for one wire to affect the signal in another. This is called a cross-talk fault. A special class of cross-talk faults is when a signal is connected to a wire that has a constant logical value (e.g., a power supply wire). In this case we have a stuck-at-0 or a stuck-at-1 fault, and the affected signal always has a logical value of 0 or 1, respectively. The following problems refer to bit 0 of the Write Register input on the register file in Figure 4.24. (a) P&H(4.6.1) <§4.3,4.4> Let us assume that the processor testing is done by filling the PC, registers, and data and instruction memories with some values (you can choose which sw