Shown in figure shows that even when the output b is

shown in Figure shows that even when the output b is set to -1V, the system still spikes because V is
already at Vth=1V (from equation 7).
Figure 7: LTSpice Behavioral Model of a QIF neuron with 1/RC=10, Vpeak=2V, Vreset=-1V, and B a pulse that goes to -1V from .1V at 800ms.
Figure 8: Transient response of a QIF neuron with 1/RC=10, Vpeak=2V, Vreset=-1V, and B a pulse that goes to -1V from .1V at 800ms.
Figure and Figure show that if the output does not reach Vth before the input is switched back to -
1V the circuit does not spike.

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Figure 9: LTSpice Behavioral Model of a QIF neuron with 1/RC=10, Vpeak=2V, Vreset=-1V, and B a pulse that goes to -1V from .1V at 700ms.
Figure 10: Transient response of a QIF neuron with 1/RC=10, Vpeak=2V, Vreset=-1V, and B a pulse that goes to -1V from .1V at 700ms.
The input variable b, can also be a slow ramp function. Figure and Figure show that the spiking rate
increases and decreases as b is raised above zero. This might make one ting that a QIF neuron is just
a PWM scheme with a fancy name.
Figure 11: LTSpice Behavioral Model of a QIF neuron with 1/RC=100, Vpeak=2V, Vreset=-1V, and B a slow ramp that goes from -1V to 1V and back
every 2s.

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Figure 12: Transient resonse of a QIF neuron with 1/RC=100, Vpeak=2V, Vreset=-1V, and B a slow ramp that goes from -1V to 1V and back every 2s.
Figure and Figure shows that even though if Vreset is less than Vth , and b is greater than zero V the
QIF does act like a PWM scheme, the situation changes if Vreset is greater than Vth. Notice that
from about .7 seconds onward the frequency of spiking increases but on the down side the frequency
of spiking decreases is does not stop until much later. This feature is called bistability.
Figure 13: LTSpice Behavioral Model of a of a QIF neuron with 1/RC=10, Vpeak=2V, Vreset=.5V, and B a slow ramp that goes from -1V to 1V and back
every 2s.
Figure 14: Transient response of a QIF neuron with 1/RC=10, Vpeak=2V, Vreset=.5V, and B a slow ramp that goes from -1V to 1V and back every 2s.
Objective
For the first week:

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1. Repeat figures 1-10 in LTspice
2. Design a circuit that implements equation 1, Check:
a. VOS
b. Slew Rate of opamp and multiplier
3. The reset condition needs a Schmitt trigger to implement an idea for this can be
seen in XX
Figure 15: Resettable inverting integrator. The IC is fed into an inverting summing amplifier, and the out put is then fed into an inverting Schmitt trigger.
The output of the Schmitt trigger V(tt) is then fed to two pmos transistors. When V(tt) goes negative the PMOS transistors pull V(t) and V(t1) to zero volts.
Pre-Lab
Research analog implementations of the quadratic integrate and fire circuit.
Lab Exercise