4 28 tdo not driven by shift register chain test 855

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Cell Driven by Inactive Element [TEST-854]. . . . . . . . . . . . . . . . . . . . . . . . 4-28 TDO Not Driven by Shift Register Chain [TEST-855] . . . . . . . . . . . . . . . . . 4-28 TDO Port Not Enabled [TEST-856]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 BSR Cannot Update [TEST-861] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 TDO Port Driven by Constant Source [TEST-864] . . . . . . . . . . . . . . . . . . . 4-29 TDO Port Not Enabled During Shift_DR [TEST-865] . . . . . . . . . . . . . . . . . 4-29 Values At The TDO Pin [TEST-1110] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 Pad Cell Is Missing At The TDO Port [TEST-1110a]. . . . . . . . . . . . . . . . . . 4-29 Values At The Pins Of The Shift Flip-Flop [TEST-1111] . . . . . . . . . . . . . . . 4-29 Break In Shift Register Chain Caused By Unknown Value Of Pin [TEST-1112] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Break In Shift Register Chain Caused By A Feedback Loop [TEST-1113]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 TDO Port Is Driven By The Shift Flip-Flop [TEST-1114] . . . . . . . . . . . . . . . 4-30 Data Is Inverted Between TDI And TDO [TEST-1115] . . . . . . . . . . . . . . . . 4-30 Instruction Register Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 Cannot Access Instruction Register [TEST-825] . . . . . . . . . . . . . . . . . . . . 4-31 Instruction Register Length [TEST-826] . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Least Significant Bit Loading [TEST-828] . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 Instruction Register Updates on Rising Edge of TCK [TEST-844] . . . . . . . 4-31 Shift_IR Flip-Flops Not Clocked on Rising Edge of TCK [TEST-851]. . . . . 4-32 Instruction Register Updates on Rising Edge of TCK but Might Not in the Update IR Control State [TEST-858]. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Bypass Register Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Cannot Access Registers in Test-Logic-Reset State [TEST-830a] . . . . . . . 4-32 Cannot Access Bypass Register [TEST-832] . . . . . . . . . . . . . . . . . . . . . . . 4-33 All-Ones Opcode Selects Multibit Bypass Register [TEST-880]. . . . . . . . . 4-33 Invalid Bypass Register Capture Value [TEST-881] . . . . . . . . . . . . . . . . . . 4-33 Device Identification Register Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 Incorrect ID Register Length [TEST-829] . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34
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Contents xi BSD Compiler Reference Manual Version N-2017.09 Least Significant Bit Capture Value Should Be Logic 1 [TEST-835]. . . . . . 4-34 Invalid Manufacturer Code [TEST-836] . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34 Boundary-Scan Register Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 BSR Is Updated on Rising Edge of TCK [TEST-846] . . . . . . . . . . . . . . . . . 4-35 BSR Cells on Design Port Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Missing BSR Cells on Design Input Port [TEST-838] . . . . . . . . . . . . . . . . . 4-36 Missing BSR Cells on Design Output Port [TEST-838a] . . . . . . . . . . . . . . 4-36 BSR Cell Placed on TAP Port [TEST-839] . . . . . . . . . . . . . . . . . . . . . . . . . 4-36 BSR Cell Placed on Compliance Port [TEST-840] . . . . . . . . . . . . . . . . . . . 4-37 Logic Exists Between BSR Cell and Design Port [TEST-843] . . . . . . . . . . 4-37 Tristate Pin Has Multiple BSR Controlling Cells [TEST-849] . . . . . . . . . . . 4-37 BSR Cell Improperly Merged: Unnecessary Merging [TEST-860] . . . . . . . 4-37 BSR Cell Improperly Merged: Too Many Functions [TEST-860a]. . . . . . . . 4-37 Input BSR Cell At Bidirectional Port Not Detected; Missing Control BSR Cell [TEST-1121] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 Input BSR Cell Not Detected At Port Due To Pad Not Propagating Data [TEST-1122] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 Output BSR Cell Not Detected Because Pad Cannot Propagate Data [TEST-1123] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 BSR Cell %s On Port %s Not Detected Because Control Cell Not Found At Port [TEST-1124]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 Cannot Find BSR Cell At Port Caused By BSR Cell Update Stage Flip-Flop [TEST-1125]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 Phase Three: Extracting Implemented Instructions and Test Data Registers. . . . . . 4-39 Phase Three Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Extracting Decoding Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40 Building an Opcode Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 Analyzing and Classifying Signatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 Inferring the SAMPLE and PRELOAD Instructions . . . . . . . . . . . . . . . . . . 4-41 Inferring Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42 SAMPLE and PRELOAD Instruction Messages . . . . . . . . . . . . . . . . . . . . . . . . 4-43 Opcode Does Not Select Register [TEST-837]. . . . . . . . . . . . . . . . . . . . . . 4-44 Missing SAMPLE/PRELOAD Instruction [TEST-841]. . . . . . . . . . . . . . . . . 4-44 BSR Cell Cannot Capture Logic State of Input Port [TEST-875] . . . . . . . . 4-44 Unable to Locate Parallel Input for BSR Cell [TEST-890]. . . . . . . . . . . . . . 4-44 Unable to Locate Parallel Output for BSR Cell [TEST-891] . . . . . . . . . . . . 4-45 Mandatory SAMPLE Instruction Not Implemented [TEST-896] . . . . . . . . .
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