Fundamentals-of-Microelectronics-Behzad-Razavi.pdf

10175 10176 where the term represents the

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(10.175) (10.176) where the term represents the transconductance of the parallel combination of and . This quantity is called the “common-mode gain.” These observations apply to the MOS counter- part equally well. An alternative approach to arriving at (10.175) is outlined in Problem 65. In summary, if the tail current exhibits a finite output impedance, the differential pair pro- duces an output CM change in response to an input CM change. The reader may naturally wonder whether this is a serious issue. After all, so long as the quantity of interest is the dif- ference between the outputs, a change in the output CM level introduces no corruption. Figure 10.44(a) illustrates such a situation. Here, two differential inputs, and , experience some common-mode noise, . As a result, the base voltages of and with respect to ground appear as shown in Fig. 10.44(b). With an ideal tail current source, the input CM variation would have no effect at the output, leading to the output waveforms shown in Fig. 10.44(b). On the other hand, with , the single-ended outputs are corrupted, but not the differential output [Fig. 10.44(c)]. In summary, the above study indicates that, in the presence of input CM noise, a finite CM gain does not corrupt the differential output and hence proves benign. However, if the circuit suffers from asymmetries and a finite tail current source impedance, then the differential output is corrupted. During manufacturing, random “mismatches” appear between the two sides of the differential pair; for example, the transistors or the load resistors may display slightly different dimensions. Consequently, the change in the tail current due to an input CM variation may affect the differential output. As an example of the effect of asymmetries, we consider the simple case of load resistor mismatch. Depicted in Fig. 10.45(a) for a MOS pair, this imperfection leads to a difference between and . We must compute the change in and and multiply the result by and . Interestingly, older literature has considered this effect troublesome. We have chosen a MOS pair here to show that the treatment is the same for both technologies.
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 507 (1) Sec. 10.5 Common-Mode Rejection 507 Q Q 1 2 R V I EE CC P C R C out1 out2 R EE CM in2 in1 A B A B out1 out2 out1 out2 t A B out1 out2 out1 t (c) (a) (b) V V V V V V V V V V V out2 V V V V V V Figure 10.44 (a) Differential pair sensing input CM noise, (b) effect of CM noise at output with , (c) effect of CM noise at the output with . R V I P R out1 out2 R CM M 1 M 2 V D D D R + DD SS SS V V V Figure 10.45 MOS pair with asymmetric loads. How do we determine the change in and ? Neglecting channel-length modulation, we first observe that (10.177) (10.178) concluding that must be equal to because and hence . In other words, the load resistor mismatch does not impact the symmetry of currents carried by and . Writing and , we recognize that both and flow through , creating a voltage change of But with , it would.
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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 508 (1) 508 Chap. 10
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