Minimizing number of stages is not always fastest

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Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverter D = 1 1 1 1 64 64 64 64 InitialDriver DatapathLoad N: f: D: 1 2 3 4
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Digital IC 40 Best Number of Stages How many stages should a path use? Minimizing number of stages is not always fastest Example: drive 64-bit datapath with unit inverter D = NH 1/N + P = N(64) 1/N + N 1 1 1 1 8 4 16 8 2.8 23 64 64 64 64 Initial Driver Datapath Load N: h: D: 1 64 65 2 8 18 3 4 15 4 2.8 15.3 Fastest
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Digital IC 41 Derivation Consider adding inverters to end of path How many give least delay? Define best stage effort N - n 1 ExtraInverters Logic Block: n 1 Stages Path Effort F 0 ln ) ( 1 1 1 1 1 1 1 inv N N N inv n i i N p H H H N D p n N p NH D 0 ) ln 1 ( 1 inv N p h h H h
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Digital IC 42 Best Stage Effort has no closed-form solution Neglecting parasitics (p inv = 0), we find h = 2.718 (e) For p inv = 1, solve numerically for h = 3.59 0 ) ln 1 ( h h p inv ) (log log ) ( log 1 1 1 1 1 1 n H p H h n N p Nh D H N h n i i h n i i h
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Digital IC 43 Sensitivity Analysis How sensitive is delay to using exactly the best number of stages? 2.4 < h < 6 gives delay within 15% of optimal We can be sloppy! I like h = 4 1.0 1.2 1.4 1.6 1.0 2.0 0.5 1.4 0.7 N / N 1.15 1.26 1.51 ( =2.4) ( =6) D(N) / D(N) 0.0
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Digital IC Example, Revisited Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? 44 A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
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Digital IC 45 Number of Stages Decoder effort is mainly electrical and branching Electrical Effort: F = Branching Effort: B = If we neglect logical effort (assume G = 1) Path Effort: H = Number of Stages: N = Try a 3-stage design
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Digital IC 46 Number of Stages Decoder effort is mainly electrical and branching Electrical Effort: F= (32*3) / 10 = 9.6 Branching Effort: B = 8 If we neglect logical effort (assume G = 1) Path Effort: H = GBF = 76.8 Number of Stages: N = log 4 H = 3.1 Try a 3-stage design
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Digital IC 47 Gate Sizes & Delay Logical Effort: G = Path Effort: H = Stage Effort: h= Path Delay: D = Gate sizes: z = y = A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0] word[0] word[15] 96 units of wordline capacitance 10 10 10 10 10 10 10 10 y z y z
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Digital IC 48 Gate Sizes & Delay Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: H = GBF = 154 Stage Effort: h =H 1/3 =5.36 Path Delay: D =3h+1+4+1=22.1 Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7 A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0] word[0] word[15] 96 units of wordline capacitance 10 10 10 10 10 10 10 10 y z y z
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