chapter4-comlogic02

# Y d0 s d1 s y d0 s d1 s f b 1 n 2 pk digital ic 64

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Y D0 S D1 S Y D0 S D1 S F = 160 / 16 = 10 B = 1 N = 2 PK

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Digital IC 64 NAND Solution Y D0 S D1 S 4 . 12 4 2 * 2 . 4 2 . 4 9 160 9 16 3 4 3 4 4 2 2 P Nh D H h GBF H G P N
Digital IC 65 Compound Solution Y D0 S D1 S

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Digital IC 66 Compound Solution Y D0 S D1 S 14 4 2 * 5 . 4 5 . 4 20 2 1 3 6 5 1 4 P Nh D H h GBF H G P N
Digital IC 67 Example 5 Annotate your designs with transistor sizes that achieve this delay. Y Y

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Digital IC 68 Example 5 Annotate your designs with transistor sizes that achieve this delay. 6 6 6 6 10 10 Y 24 12 10 10 8 8 8 8 8 8 8 8 25 25 25 25 Y 16 16 160 * (4/3) / 4.2 = 50 160 * 1 / 4.5 = 36
Digital IC 69 Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same g A = g B = g total = Asymmetric gate approaches g = 1 on critical input But total logical effort goes up A reset Y 4 4/3 2 2 reset A Y

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Digital IC 70 Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same g A = 10/9 g B = 2 g total = g A + g B = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up A reset Y 4 4/3 2 2 reset A Y
Digital IC Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nMOS transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. gu = gd = 71 1/2 2 A Y 1 2 A Y 1/2 1 A Y HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance)

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Digital IC Skewed Gates Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nMOS transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u = 2.5 / 3 = 5/6 g d = 2.5 / 1.5 = 5/3 72 1/2 2 A Y 1 2 A Y 1/2 1 A Y HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance)
Digital IC 73 HI- and LO-Skew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS) Logical effort is smaller for favored direction But larger for the other direction

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Digital IC 74 Catalog of Skewed Gates 1/2 2 A Y Inverter B A Y B A NAND2 NOR2 HI-skew LO-skew 1 1 A Y B A Y B A g u = 5/6 g d = 5/3 g avg = 5/4 g u = 4/3 g d = 2/3 g avg = 1 g u = g d = g
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