Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi- tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The external memory interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are: • D to Q propagation delay (t pd ). • Data setup time before G low (t su ). • Data (address) hold time after G low ( th ). The external memory interface is designed to guaranty minimum address hold time after G is asserted low of t h = 5 ns (refer to t LAXX_LD /t LLAXX_ST in Table 114 to Table 121 on page 272 ). The D to Q propagation delay (t pd ) must be taken into consideration when calculating the access time requirement of the external component. The data setup time before G low (t su ) must not exceed address valid to ALE low (t AVLLC ) minus PCB wiring delay (dependent on the capacitive load). Figure 12. External SRAM Connected to the AVR D[7:0] A[7:0] A[15:8] RD WR SRAM D Q G AD7:0 ALE A15:8 RD WR AVR
28 2513L–AVR–03/2013 ATmega162/V Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus keeper on the AD7:0 lines. The Bus Keeper can be dis- abled and enabled in software as described in “Special Function IO Register – SFIOR” on page 32 . When enabled, the Bus Keeper will keep the previous value on the AD7:0 bus while these lines are tri-stated by the XMEM interface. Timing External memory devices have various timing requirements. To meet these requirements, the ATmega162 XMEM interface provides four different wait-states as shown in Table 3 . It is impor- tant to consider the timing specification of the external memory device before selecting the wait- state. The most important parameters are the access time for the external memory in conjunc- tion with the set-up requirement of the ATmega162. The access time for the external memory is defined to be the time from receiving the chip select/address until the data of this address actu- ally is driven on the bus. The access time cannot exceed the time from the ALE pulse is asserted low until data must be stable during a read sequence (t LLRL + t RLRH - t DVRH in Table 114 to Table 121 on page 272 ). The different wait-states are set up in software. As an additional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings.
You've reached the end of your free preview.
Want to read all 324 pages?
- Spring '16
- Central processing unit, X86, Processor register, EEPROM