If the XRS signal is low when WDRST goes high then the WDFLAG bit remains at 0

If the xrs signal is low when wdrst goes high then

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high. If the XRS signal is low when WDRST goes high, then the WDFLAG bit remains at 0. In a typical application, the WDRST signal connects to the XRS input. Hence to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration then the watchdog pulse. 5.5 32-Bit CPU Timers 0/1/2 This section describes the three 32-bit CPU timers ( Figure 31 ) (TIMER0/1/2). CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for DSP/BIOS. If the application is not using DSP/BIOS, then Timer 2 can be used in the application. The CPU-timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 32 . Figure 31. CPU Timers 55 SPRUFB0D–September 2007–Revised March 2010 Flash and OTP Memory Blocks Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated
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INT1 to INT12 INT14 28x CPU TINT2 TINT0 PIE CPU-TIMER 0 CPU-TIMER 2 (Reserved for DSP/BIOS) INT13 TINT1 CPU-TIMER 1 XINT13 Clocking and System Control Figure 32. CPU-Timer Interrupt Signals and Output Signal A The timer registers are connected to the Memory Bus of the 28x processor. B The timing of the timers is synchronized to SYSCLKOUT of the processor clock. The general operation of the CPU timer is as follows: The 32-bit counter register TIMH:TIM is loaded with the value in the period register PRDH:PRD. The counter decrements once every (TPR[TDDRH:TDDR]+1) SYSCLKOUT cycles where TDDRH:TDDR is the timer divider. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 31 are used to configure the timers. Table 31. CPU Timers 0, 1, 2 Configuration and Control Registers Name Address Size (x16) Description Bit Description TIMER0TIM 0x0C00 1 CPU-Timer 0, Counter Register Figure 33 TIMER0TIMH 0x0C01 1 CPU-Timer 0, Counter Register High Figure 34 TIMER0PRD 0x0C02 1 CPU-Timer 0, Period Register Figure 35 TIMER0PRDH 0x0C03 1 CPU-Timer 0, Period Register High Figure 36 TIMER0TCR 0x0C04 1 CPU-Timer 0, Control Register Figure 37 Reserved 0x0C05 1 TIMER0TPR 0x0C06 1 CPU-Timer 0, Prescale Register Figure 38 TIMER0TPRH 0x0C07 1 CPU-Timer 0, Prescale Register High Figure 39 TIMER1TIM 0x0C08 1 CPU-Timer 1, Counter Register Figure 33 TIMER1TIMH 0x0C09 1 CPU-Timer 1, Counter Register High Figure 34 TIMER1PRD 0x0C0A 1 CPU-Timer 1, Period Register Figure 35 TIMER1PRDH 0x0C0B 1 CPU-Timer 1, Period Register High Figure 36 TIMER1TCR 0x0C0C 1 CPU-Timer 1, Control Register Figure 37 Reserved 0x0C0D 1 TIMER1TPR 0x0C0E 1 CPU-Timer 1, Prescale Register Figure 38 TIMER1TPRH 0x0C0F 1 CPU-Timer 1, Prescale Register High Figure 39 TIMER2TIM 0x0C10 1 CPU-Timer 2, Counter Register Figure 33 TIMER2TIMH 0x0C11 1 CPU-Timer 2, Counter Register High Figure 34 TIMER2PRD 0x0C12 1 CPU-Timer 2, Period Register Figure 35 TIMER2PRDH 0x0C13 1 CPU-Timer 2, Period Register High Figure 36 TIMER2TCR 0x0C14 1 CPU-Timer 2, Control Register Figure 37 Reserved 0x0C15 1 TIMER2TPR 0x0C16 1 CPU-Timer 2, Prescale Register Figure 38 TIMER2TPRH 0x0C17 1 CPU-Timer 2, Prescale Register High Figure 39 56
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