Appendix A: Using GUI Tools
Analyzing Timing Paths
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IC Compiler Implementation User Guide
D-2010.03-SP4
IC Compiler Implementation User Guide
Version D-2010.03-SP4
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To display the current edit cell by itself in the layout view, deselect the “Edit in Place”
option.
By default, this option is selected and the layout view displays the current edit cell in
its place within the primary design. If you deselect this option, the layout view displays
the current edit cell in its normal orientation regardless of its orientation within the
primary design. For information about the primary design in a layout window, see
“Setting the Primary Design” on page 2-35
.
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To set the brightness level for objects outside the current edit cell when the “Edit in
Place” option is selected, select an option in the brightness () list.
3.
Click Apply.
If you open multiple layout views in the same layout window, all the layout views have the
same current edit cell. If you want to edit different cells at the same time, you must open
them in different layout windows.
If the error browser is open when you change the current edit cell, the tool automatically
loads the editor DRC error view for the new current design, if it exists, into the error browser
editor DRC view. Only error views associated with the current design can be loaded in the
error browser. However, regardless of which design is the current design, the layout view
continues to display of error shapes for any design that is open in the layout window.
If Hercules VUE is open when you change the current edit cell, the layout view continues to
display DRC errors in the primary design. However, you should load the errors for the current
edit cell if you want the layout view to interpret coordinates from Hercules VUE in the correct
coordinate space.
For more information about using the edit-in-place facility in a layout window, see the IC
Compiler online Help.
Analyzing Timing Paths
The timing analysis window provides a centralized area for performing timing path analysis.
The window includes a timing analysis driver, a path inspector, and other analysis tools such
as histograms, schematics, path profiles, and timing reports.
You can use tools in the timing analysis window to perform both high-level and detailed
analyses of the timing paths in your design. You can
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Examine timing path details in the timing analysis driver
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View histograms that show the distribution of worst path slack, endpoint slack, net
capacitance, or other path details in histogram views
