1 r3 r3 op r5 r3 3 r3 r5 1 r3 r3 r3 r3 2005 mikko

This preview shows page 8 - 15 out of 45 pages.

(1) R3 R3 op R5 R3 (3) R3 R5 + 1 R3 <= … <= R3 R3’ <= … <= R3’
Image of page 8

Subscribe to view the full document.

© 2005 Mikko Lipasti 9 Register Renaming Register Renaming Resolves: Anti-Dependences Output Dependences Design of Redundant Registers : Number: One Multiple Allocation: Fixed for Each Register Pooled for all Regsiters Location: Attached to Register File (Centralized) Attached to functional units (Distributed) Architected Physical Registers Registers R1 R2 Rn P1 P2 Pn Pn + k
Image of page 9
© 2005 Mikko Lipasti 10 Register Renaming in the RIOS-I FPU FPU Register Renaming Map table 32 x 6 32 33 34 35 36 37 38 39 Free List head tail head tail release Pending Target Return Queue FAD 3 2 1 FAD 3 2 1 OP T S1 S2 S3 OP T S1 S2 S3 Incoming FPU instructions pass through a renaming table prior to decode The 32 architectural registers are remapped to 40 physical registers Physical register names are used within the FPU Complex control logic maintains active register mapping Simplified FPU Register Model Fload R7 <= Mem[] (P32 alloc) R7: P32 7 Free when Fload R7 commits Fload R7 <= Mem[] (P32 freed) <= R7 (actual last use) (P32)
Image of page 10

Subscribe to view the full document.

© 2005 Mikko Lipasti 11 Resolving True Data Dependences STALL DISPATCHING ADVANCE INSTRUCTIONS “DYNAMIC EXECUTION” Reservation Station + Complex Forwarding Out-of-order (OoO) Execution Try to Approach the “Data-Flow Limit” REGISTER READ ALU OP REGISTER WRITE (1) R2 R1 + 1 (2) R3 R2 (3) R4 R3 1) Read register(s), get “IOU” if not ready 2) Advance to reservation station 3) Wait for “IOU” to show up 4) Execute
Image of page 11
© 2005 Mikko Lipasti 12 Embedded “Data Flow” Engine Dispatch Buffer Reservation Dispatch Complete Stations “Dynamic Completion Buffer Branch Execution” - Read register or - Assign register tag - Monitor reg. tag - Receive data being forwarded - Issue when all operands ready - Advance instructions to reservation stations
Image of page 12

Subscribe to view the full document.

Tomasulo’s Algorithm [Tomasulo, 1967] Ctrl. Adder Decoder Floating Point Registers (FLR) Control 0 2 4 8 Control Floating Operand Stack (FLOS) Floating Point Buffers (FLB) 1 2 3 4 5 6 Store Data 1 2 3 Buffers (SDB) Control Storage Bus Ctrl. Adder Instruction Unit To Storage Result Sink Source Adder Multiply/Divide Result Sink Source Floating Point Register (FLR) Bus Floating Point Buffer (FLB) Bus Result Bus
Image of page 13
IBM 360/91 FPU Multiple functional units (FU’s) Floating-point add Floating-point multiply/divide Three register files (pseudo reg-reg machine in floating-point unit) (4) floating-point registers (FLR) (6) floating-point buffers (FLB) (3) store data buffers (SDB) Out of order instruction execution : After decode the instruction unit passes all floating point instructions (in order) to the floating-point operation stack (FLOS) [actually a queue, not a stack] In the floating point unit, instructions are then further decoded and issued from the FLOS to the two FU’s Variable operation latencies : Floating-point add: 2 cycles Floating-point multiply: 3 cycles Floating-point divide: 12 cycles Goal: achieve concurrent execution of multiple floating-point instructions, in addition to achieving one instruction per cycle in instruction pipeline
Image of page 14

Subscribe to view the full document.

Image of page 15
You've reached the end of this preview.
  • Fall '09
  • PROFGURISOHI
  • Processor register, Register renaming, Tomasulo algorithm, Register file, Out-of-order execution

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern