The watchdog module generates an output pulse 512 oscillator clocks wide OSCCLK

The watchdog module generates an output pulse 512

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The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-13 shows the various functional blocks within the watchdog module. A. The WDRST signal is driven low for 512 OSCCLK cycles. Figure 3-13. Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7 , Low-Power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG. 62 Functional Overview Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 3.7 Low-Power Modes Block The low-power modes on the 2833x/2823x devices are similar to the 240x devices. Table 3-19 summarizes the various modes. Table 3-19. Low-Power Modes MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT EXIT (1) XRS, Watchdog interrupt, any enabled IDLE 00 On On On (2) interrupt, XNMI On XRS, Watchdog interrupt, GPIO Port A STANDBY 01 Off Off (watchdog still running) signal, debugger (3) , XNMI Off XRS, GPIO Port A signal, XNMI, HALT 1X (oscillator and PLL turned off, Off Off debugger (3) watchdog not functional) (1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the IDLE mode will not be exited and the device will go back into the indicated low power mode. (2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is still functional while on the 24x/240x the clock is turned off. (3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register.
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