23 24 Conceptually a smart dust mote consists of several MEMS sensors a solar

23 24 conceptually a smart dust mote consists of

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23 24 Conceptually, a smart dust mote consists of several MEMS sensors, a solar cell, optical communication, and a microcontroller. The microcontroller is a load-store RISC processor with a Harvard architecture (separate instruction and data mem- ories). Figure 1 presents a functional block diagram of the system. The design incorporates a continuously run- ning low-speed oscillator that drives five on-chip timers for sensor sampling, radio transmission and reception, and CLKS 10 KHz CLK 100 KHz Datapath ... Sensor Radio: receive Radio: transmit Timer compare register Timer compare register Timer compare register Timer compare register Real time clock Controller (nominally asleep) Oscillator Oscillator Fig. 1. Smart dust microarchitecture. Reprinted with permission from [23], B. A. Warneke and K. S. J. Pister, An ultra-low energy microcon- troller for smart dust wireless sensor networks. ISSCC , January (2004) . © 2004. data path operation. When the timers fire, a faster oscil- lator is powered on to drive the datapath and ADC. By including independent subsystems (each driven by its own timer) the system is able to clock-gate inactive blocks. However the system is not natively event driven and uses the timers to poll the data sources periodically. This sys- tem was designed in 0.25 m technology and consequently did not need to address leakage current with architecture. At 1.0 V and 500 kHz the system consumes 12 pJ per instruction. 4.3. Subthreshold Systems As presented in Section 2, the throughput requirements of nodes for WSNs depend on the observed phenomena. For phenomena requiring low frequency sampling (less than 100 Hz), off-the-shelf systems easily keep up with the required real-time workloads resulting in long idle times. Several researchers have designed circuits that oper- ate below the threshold voltage which trades performance for power consumption. Several system building blocks that run in subthreshold have been presented, including an FFT. 22 Researchers at Michigan have designed one of the first complete processors for WSNs designed to run in sub- threshold, the Subliminal Processor . 8 16 17 28 Both versions of the system center around a traditional general purpose Harvard based architecture. The authors swept several dif- ferent architecture parameters such as register size, bus width, CISC/RISC, and number of pipeline stages. The authors evaluated code size, cycles-per-instruction (CPI), and energy. 17 The architecture of version two of the Subliminal pro- cessor is presented in Figure 2. The system consists of an IF/ID EX/MEM WB To RF Decode + control logic Scheduler + fetch control Data memory 128×8 ALU Register File 8×8 Register File 4×12 Instruction memory 128×12 2×12 Register write control logic 8 8 8 8 CORE Fig. 2. Block diagram of the subliminal processor (University of Michigan). Reprinted with permission from [8], S. Hanson et al., Per- formance and variability optimization strategies in a Sub-200 mV, 3.5 pJ/inst, 11 nW subthreshold processor. IEEE Symposium on VLSI Circuits (VLSI-Symp) , June (2007) . © 2007. J. Low Power Electronics 4, 1–10, 2008 5
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  • Fall '18
  • Mr. Bhullar
  • Sensor node, Wireless sensor network

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