Of course the students should understand that this is

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ing five extra stages would increase the minimum to 40 registers. Of course, the students should understand that this is a minimum that assumes no data dependences or cache misses. At the same time, it also assumes throughput of 4 IPC. Since few processors achieve 4 IPC on real programs due to data dependences, control dependences, and cache misses, this “minimum” may in fact be sufficient. The only reliable way to determine the right number of rename registers is a sensitivity study using detailed simulation of a range of rename reg- isters to find the knee in the performance curve. Problem 6 14. Identify basic blocks: Structure Offset bits Index bits Tag bits Size of tag array Size of data array I-cache 7 7 18 512x(18 tag + 1 valid) = 9728 bits 64KB D-cache 6 8 22 512x(22+1 valid + 1 dirty) = 12,288 bits 32KB TLB 12 5 15 128x(15 tag + v) = 2048 bits 128x(24+d+r +3p) = 3712 bits BB# 1 2 3 4 5 6 7 8 9 Instr. #s 1-6 7-9 10-11 12 13-17
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