CS350 Operating Systems Winter 2014 Virtual Memory 6 Address Space Diagram for

Cs350 operating systems winter 2014 virtual memory 6

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CS350 Operating Systems Winter 2014 Virtual Memory 6 Address Space Diagram for Paging 2 m -1 0 Proc 1 virtual address space 0 max1 virtual address space Proc 2 physical memory max2 0 CS350 Operating Systems Winter 2014 74
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Virtual Memory 7 Paging Mechanism m bits register page table base v bits m bits frame # offset page # offset virtual address physical address frame # page table protection and other flags CS350 Operating Systems Winter 2014 Virtual Memory 8 Memory Protection during address translation, the MMU checks to ensure that the process uses only valid virtual addresses typically, each PTE contains a valid bit which indicates whether that PTE contains a valid page mapping the MMU may also check that the virtual page number does not index a PTE beyond the end of the page table the MMU may also enforce other protection rules typically, each PTE contains a read-only bit that indicates whether the corresponding page may be modified by the process if a process attempts to violated these protection rules, the MMU raises an exception, which is handled by the kernel The kernel controls which pages are valid and which are protected by setting the contents of PTEs and/or MMU registers. CS350 Operating Systems Winter 2014 75
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Virtual Memory 9 Roles of the Kernel and the MMU (Summary) Kernel: manage MMU state on address space switches (context switch from thread in one process to thread in a different process) create and manage page tables manage (allocate/deallocate) physical memory handle exceptions raised by the MMU MMU (hardware): translate virtual addresses to physical addresses check for and raise exceptions when necessary CS350 Operating Systems Winter 2014 Virtual Memory 10 Remaining Issues translation speed: Address translation happens very frequently. (How frequently?) It must be fast. sparseness: Many programs will only need a small part of the available space for their code and data. the kernel: Each process has a virtual address space in which to run. What about the kernel? In which address space does it run? CS350 Operating Systems Winter 2014 76
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Virtual Memory 11 Speed of Address Translation Execution of each machine instruction may involve one, two or more memory operations one to fetch instruction one or more for instruction operands Address translation through a page table adds one extra memory operation (for page table entry lookup) for each memory operation performed during instruction execution Simple address translation through a page table can cut instruction execution rate in half. More complex translation schemes (e.g., multi-level paging) are even more expensive. Solution: include a Translation Lookaside Buffer (TLB) in the MMU TLB is a fast, fully associative address translation cache TLB hit avoids page table lookup CS350 Operating Systems Winter 2014 Virtual Memory 12 TLB Each entry in the TLB contains a (page number, frame number) pair.
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