100%(2)2 out of 2 people found this document helpful
This preview shows page 75 - 79 out of 168 pages.
CS350Operating SystemsWinter 2014Virtual Memory6Address Space Diagram for Paging2m-10Proc 1 virtual address space0max1virtual address spaceProc 2physical memorymax20CS350Operating SystemsWinter 201474
Virtual Memory7Paging Mechanismm bitsregisterpage table basev bitsm bitsframe #offsetpage #offsetvirtual addressphysical addressframe #page tableprotection andother flagsCS350Operating SystemsWinter 2014Virtual Memory8Memory Protection•during address translation, the MMU checks to ensure that the process usesonlyvalidvirtual addresses–typically, each PTE contains avalid bitwhich indicates whether that PTEcontains a valid page mapping–the MMU may also check that the virtual page number does not index a PTEbeyond the end of the page table•the MMU may also enforce other protection rules–typically, each PTE contains aread-onlybit that indicates whether thecorresponding page may be modified by the process•if a process attempts to violated these protection rules, the MMU raises anexception, which is handled by the kernelThe kernel controls which pages are valid and which are protected by settingthe contents of PTEs and/or MMU registers.CS350Operating SystemsWinter 201475
Virtual Memory9Roles of the Kernel and the MMU (Summary)•Kernel:–manage MMU state on address space switches (context switch from threadin one process to thread in a different process)–create and manage page tables–manage (allocate/deallocate) physical memory–handle exceptions raised by the MMU•MMU (hardware):–translate virtual addresses to physical addresses–check for and raise exceptions when necessaryCS350Operating SystemsWinter 2014Virtual Memory10Remaining Issuestranslation speed:Address translation happens very frequently. (How frequently?)It must be fast.sparseness:Many programs will only need a small part of the available space fortheir code and data.the kernel:Each process has a virtual address space in which to run. What aboutthe kernel? In which address space does it run?CS350Operating SystemsWinter 201476
Virtual Memory11Speed of Address Translation•Execution of each machine instruction may involve one, two or more memoryoperations–one to fetch instruction–one or more for instruction operands•Address translation through a page table adds one extra memory operation (forpage table entry lookup) for each memory operation performed duringinstruction execution–Simple address translation through a page table can cut instruction executionrate in half.–More complex translation schemes (e.g., multi-level paging) are even moreexpensive.•Solution: include a Translation Lookaside Buffer (TLB) in the MMU–TLB is a fast, fully associative address translation cache–TLB hit avoids page table lookupCS350Operating SystemsWinter 2014Virtual Memory12TLB•Each entry in the TLB contains a (page number, frame number) pair.