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# Make pmos about ¼ effective strength of pulldown 09

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– Make pMOS about ¼ effective strength of pulldown network 0 0.3 0.6 0.9 1.2 1.5 1.8 0 0.3 0.6 0.9 1.2 1.5 1.8 P = 24 P = 4 P = 14 V in V out V out V in 8/2 P/2 I ds load Logical Effort: Pseudo-nMOS Gates PMOS width is ¼ the strength of the NMOS pulldown network Pull-up drive current –I P =W EFF_P P N ) Pull-down drive current – For the high-to-low transition, PMOS transistor fights the NMOS transistors in pull-down network N -I P =W EFF_N -W EFF_P P N ) Inverter NAND2 NOR2 4/3 2/3 A Y 8/3 8/3 2/3 B A Y AB 4/3 4/3 2/3 g u = 4/3 g d = 4/9 g avg = 8/9 Y g u = 8/3 g d = 8/9 g avg = 16/9 g u = 4/3 g d = 4/9 g avg = 8/9 Logical Effort: Pseudo-nMOS INV The logical effort of each transition is computed as the ratio of the input capacitance to that of a CMOS inverter with equivalent resistance for that transition Inverter 4/3 2/3 A Y g u = (4/3)/1=4/3 g d = (4/3)/3=4/9 g avg = 8/9 Pull-up Pull-down 1 2 AY 1/3 2/3 g u I P =(2/3)(1/2)I=I/3 R P =IR/(I/3)=3R 4/3 2/3 A Y I N =(4/3)I-(2/3)(1/2)I=I R N =IR/(I)=R g d p u = (6/3)/1=6/3 p d = (6/3)/3=6/9 p avg = 12/9

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5 Logical Effort: Pseudo-nMOS NAND2 Determine Logical Effort of Pseudo NMOS NAND2 Inverter g u = (8/3)/1=8/3 g d = (8/3)/3=8/9 g avg = 16/9 Pull-up Pull-down 1 2 AY 1/3 2/3 g u I P =(2/3)(1/2)I=I/3 R P =IR/(I/3)=3R I N =(4/3)I-(2/3)(1/2)I=I R N =IR/(I)=R g d 8/3 8/3 2/3 B A Y 8/3 8/3 2/3 B A Y p u = (10/3)/1=10/3 p d = (10/3)/3=10/9 p avg = 20/9 Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0 – Static power P = I•V DD – A few mA / gate * 1M gates would be a problem – This is why nMOS only logic went extinct! Use pseudo-nMOS sparingly for wide NORs – Logical effort of NOR is lower that NAND gates (unlike CMOS static logic) Turn off pMOS when not in use AB Y C en Cascode Voltage Switch Logic (CVSL) True and complementary input and outputs – Pull-up network simplified – Requires f and its complement function For a given input pattern one of the pulldown networks is ON and the other is OFF – The feedback mechanism ensures that the PMOS load is turned OFF when the corresponding pulldown network is ACTIVE – No static power dissipation Cascode Voltage Switch Logic (CVSL)
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