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Stop UserLevel Novice MessageLevel Detailed svfUseTime false SpiByteSwap Auto_Correction AutoInfer false SvfPlayDisplayComments false AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set todefault 6 MHz regardless of explicit arguments supplied for setting the baudrates Connecting to cable (Usb Port - USB21). Checking cable driver. File version of/nfs/sw_cmc/x86_64.EL7/tools/xilinx_14.7/14.7/ ISE_DS/ISE/bin/lin64/xusbdfwu.hex= 1030. File version of /usr/share/xusbdfwu.hex = 1030. Using libusb. Kernel release = 3.10.0-862.6.3.el7.x86_64. Max current requested during enumeration is 74 mA. Type = 0x0004. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 1028. File version of/nfs/sw_cmc/x86_64.EL7/tools/xilinx_14.7/14.7/ ISE_DS/ISE/data/xusb_xlp.hex =1303. Firmware hex file version = 1303. Downloading/nfs/sw_cmc/x86_64.EL7/tools/xilinx_14.7/14.7/ISE_DS/ ISE/data/xusb_xlp.hex. Downloaded firmware version = 1303. PLD file version = 0012h. PLD version = 0012h. Type = 0x0004. ESN option: 00001418BCD201. Identifying chain contents...’0’: : Manufacturer’s ID = Xilinx xc2vp30, Version : 1 INFO:iMPACT:1777 - Reading /nfs/sw_cmc/x86_64.EL7/tools/xilinx_14.7/14.7/ ISE_DS/ISE/virtex2p/data/xc2vp3 0.bsd... INFO:iMPACT:501 - ‘1’: Added Device xc2vp30 successfully. ----------------------------------------------------------------- ----------------------------------------------------------------- ‘1’: : Manufacturer’s ID = Xilinx xccace, Version : 0 INFO:iMPACT:1777 - Reading /nfs/sw_cmc/x86_64.EL7/tools/xilinx_14.7/14.7/ ISE_DS/ISE/acecf/data/xccace.bs d...
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57 INFO:iMPACT:501 - ‘1’: Added Device xccace successfully. ----------------------------------------------------------------- ----------------------------------------------------------------- ‘2’: : Manufacturer’s ID = Xilinx xcf32p, Version : 15 INFO:iMPACT:1777 - Reading /nfs/sw_cmc/x86_64.EL7/tools/xilinx_14.7/14.7/ ISE_DS/ISE/xcfp/data/xcf32p.bsd ... INFO:iMPACT:501 - ‘1’: Added Device xcf32p successfully. ----------------------------------------------------------------- ----------------------------------------------------------------- done. Elapsed time = 0 sec. Elapsed time = 0 sec. Elapsed time = 0 sec. Elapsed time = 0 sec. ‘3’: Loading file’/home/t/ted/SYNOPSYS_2000/Xilinx/ count3_jan_2018/count3/count3.bit’ ... done. ----------------------------------------------------------------- INFO:iMPACT:501 - ‘3’: Added Device xc2vp30 successfully. ----------------------------------------------------------------- ----------------------------------------------------------------- Maximum TCK operating frequency for this device chain: 15000000. Validating chain... Boundary-scan chain validated successfully. ‘3’: Programming device... Match_cycle = NoWait. Match cycle: NoWait LCK_cycle = NoWait. LCK cycle: NoWait done. INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 0111 1011 1000 0000 0000 0000 0000 INFO:iMPACT:579 - ‘3’: Completed downloading bit file to device. INFO:iMPACT:188 - ‘3’: Programming completed successfully. Match_cycle = NoWait. Match cycle: NoWait LCK_cycle = NoWait. LCK cycle: NoWait INFO:iMPACT - ‘3’: Checking done pin .... done. ‘3’: Programmed successfully. Elapsed time = 3 sec. ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- -----------------------------------------------------------------
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58 PART IV : Xilinx FPGA Development Board The Xilinx University Program Virtex-II Pro development board contains a Virtex-II Pro XC2VP30 FPGA device in an FF896 BGA (Ball Grid Array) package. This FPGA device has the equivalent logic capability of approximately 30 000 000 logic gates. It contains 13 969 slices ( a slice contains a RAM look-up table which is used to implement combinational logic, a slice also contains dedicated flip-flops for sequential logic implementation), 428 Kb (kilobits) of distributed RAM, over 2000 Kb of Block RAM, and 136 multipliers (18 bit x 18 bit). Figure 30 is a top view photo of the XUP Virtex-II Pro development system.
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  • Fall '12
  • Electronic design automation, Xilinx

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