There are two types of power consumption in a design: dynamic and static. IC Compiler can optimize both dynamic and static power. • Dynamic power This is the energy consumed because of the voltage or logic transitions in the design objects, such as cells, pins, and nets. The dynamic power consumption is directly proportional to the number and frequency of transitions in the design. To reduce dynamic power, IC Compiler supports power-aware clock tree synthesis. For more details see “Low-Power Clock Tree Synthesis” on page 5-10 . • Static power This is the energy dissipated even when there are no transitions in the circuit. This is also known as leakage power and depends on the device characteristics. The main contributor to static power is the sub-threshold voltage leakage in the device. At lower technology nodes, leakage power consumption contributes significantly to the total power consumption of the circuit. When you enable power optimization, IC Compiler, by default, performs leakage power optimization. To perform dynamic power optimization, you must explicitly specify the option. You can also specify the effort for each of these types of optimization. IC Compiler supports power reduction at each step of the optimization flow. For more details, see “Performing Power Optimization” on page 5-9 . The tool also supports cells with different threshold voltages on different paths. Based on the area, timing, and power constraints specified, the tool chooses the appropriate cells from the library that reduce the leakage without violating the other constraints. For more details, see “Adaptive Leakage Power Optimization” on page 5-7 . Strategies To Reduce Leakage Power Because leakage power is a function of device characteristics, reducing the leakage power involves choosing devices that dissipate lower leakage power. However the device characteristics such as the drive strength, delay, area, and leakage power are interrelated. Leakage dissipation is low when the threshold voltage is high and vice versa. Moreover, switching delay is more when threshold voltage is high. If the technology library supports cells with multiple threshold-voltages, using cells with a lower threshold-voltage for timing-critical paths and cells with a higher-threshold voltage for other paths can reduce the leakage power without violating the delay. For more details on using multiple threshold-voltage cells, see “Using Multiple Threshold-Voltage Cells” on page 5-3 . For more
Chapter 5: Power Optimization Strategies To Reduce Leakage Power 5-3 IC Compiler Implementation User Guide Version D-2010.03-SP4 details on how IC Compiler chooses cells of specific threshold-voltage to obtain maximum power reduction during various stages of optimization, see “Adaptive Leakage Power Optimization” on page 5-7 .
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- Summer '19
- Electronic design automation, clock tree, ic compiler