11 A bus organized CPPU has 16 registers with 32 bit in each an ALU and a

11 a bus organized cppu has 16 registers with 32 bit

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11. A bus-organized CPPU has 16 registers with 32-bit in each, an ALU and a destination decoder .Indicate the number of multiplexers in the bus and the size of each multiplexer? 12. What is throughput of a computer system? How are they measured? 13. Register A has 10101100. Perform a suitable logic operation on A to set the 4 th and 5 th bits without effecting other bit values. 14. Which type of architecture supports large number of instructions? Also list down the other characteristics of this architecture 15. A computer has 32-bit instructions with 12-bit address fields. If there are 250 two-address instructions, how many one-address instructions can be formulated? 16. A two-level memory hierarchy system has an average access time of 12ns. The top-level of the memory system has a hit-rate of 90 percent (0.9 hit-ratio) and an access time of 5ns. What is the access time of the lower level of the memory system? 17. Give the ANSI 32-bit format for floating point representation. Represent (–0.125) in ANSI 32-bit format. 18. State the Principle of Locality. What is temporal locality and spatial locality? 19. How many 512 x 16 KB RAM and 256 KB ROM chips are required to provide a memory capacity of 5 MB RAM and 1 MB ROM? 20. Depict the memory hierarchy of a computer system. 21. Specify two methods of aligning mantissas in floating point operations? Which method is preferable? 22. In floating point arithmetic operations state the importance of normalizing the number. 23. A magnetic disk system has the following parameters: T s = average time to position the magnetic head over a track R = rotation speed of disk in revolutions per second N t = number of bits per track N s = number of bits per sector Calculate the average time T a that it will take to read one sector.
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25. Write the formula for calculating the average access time for two-level memory hierarchy, given that H is the hit-ratio of the top level memory; t 1 and t 2 are the access time of level-1 and level-2 memory. Also, extend the formula for a three level memory hierarchy.
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  • Summer '17
  • Central processing unit

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