The examined Strong PUFs included standard Arbiter PUFs XOR Arbiter PUFs

The examined strong pufs included standard arbiter

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The examined Strong PUFs included standard Arbiter PUFs, XOR Arbiter PUFs, Lightweight Secure PUFs, and Feed-For- ward Arbiter PUFs. We also investigated the hardness of cer- tain Ring Oscillator (RO) PUF architectures [46] if used in typ- ical Strong PUF scenarios, i.e., under the presumption that their CRP-interface is publicly accessible. If nothing else, this gives us an indication for how many runs these PUFs can be used se- curely within (limited count) identi fi cation protocols à la Pappu et al. [33], [34]. Some of our main results are summarized in Table XI. We found that all examined Strong PUF candidates under a certain size and architectural complexity could be machine learned with prediction rates above 99%. These rates sometimes are above the practical silicon stability of the examined PUFs. As explained in detail Section II-G, this is not paradoxical, but a natural consequence of our evaluation methodology. For ex- ample, in silicon attacks an adversary can put the PUFs to stable ambient conditions and apply majority voting to get extremely stable CRP sets. The attacks required a number of CRPs that grows only lin- early or log-linearly in the internal parameters of the PUFs, such as their number of stages, XORs, feed-forward loops, or ring os- cillators. Apart from XOR Arbiter PUFs and Lightweight PUFs (whose training times grew quasi-exponentially in their number of XORs for large bitlengths and small to medium number of XORs ), the training times of the applied machine learning al- gorithms are low-degree polynomial, too. We also executed a very detailed proof of concept for sil- icon CRPs for the two most well-studied and commercially most relevant [9], [10] electrical Strong PUF designs, Arbiter PUFs and XOR Arbiter PUFs. In this process, more than four million CRPs collected from ASICs and FPGAs were used. The simi- larity of our results on simulated and silicon data settles a con- jecture that had been posed in earlier versions of this work [41]. It shows that the linear delay model is close to practice, and es- tablishes its use in future security analyses of any Arbiter PUF variants. Our fi ndings prohibit the use of the modeled architectures up to a certain size and complexity in typical Strong PUF proto- cols whose security rests on the unpredictability or physical un- clonability of the Strong PUF, and where the adversary can col- lect many CRPs via access to the Strong PUF’s interface or by eavesdropping protocols. Under the assumption that digital sig- nals can be probed, our results also affect the applicability of the examined Strong PUFs as building blocks in Controlled PUFs, again up to a certain size and complexity. The security of Weak PUFs is not strongly affected by our methods. As discussed in detail in Section I-B, our attacks apply to this PUF type only under the rare circumstance that a Strong PUF is employed in- side a hardware system as the Weak PUF, using only few of the many possible challenges of this Strong PUF. Most typical Weak PUFs, such as the SRAM PUF [18], Butter fl y PUF [22] or Coating PUF [47], remain unaffected by our attacks.
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