EEL6323S12-HLec05-LogicalEffort-4spp

Gate type number of inputs 1 2 3 4 n inverter nand

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Gate type Number of inputs 1 2 3 4 n Inverter NAND (n+2)/3 NOR (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 Logical effort of common gates Electrical Effort Electrical Effort: h Ratio of output to input capacitance Sometimes called fanout d = f + p = gh + p
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4 Parasitic Delay Parasitic Delay: p Independent of logic gate size and load capacitance Defined by Cdb of the output node (internal Cdb neglected) Assume Cdb is linearly proportional to transistor widths d = f + p = gh + p ( ) p gh C R C R C R C C C R C R C R d inv inv pt t inv inv in out inv inv t t inv inv abs + = + Ο৿ Ο৿ Πਏ Ξ৯ Μ৏ Μ৏ Νয় Λি = τ κ κ Inverter Parasitic Delay Define the normalized inverter parasitic delay ( p inv ) p inv is the ratio of unit diffusion capacitance and unit gate capacitance Estimate from transistor widths γ 1 IN OUT A B Y A B Y A Y 1 2 1 1 2 2 2 2 4 4 C pt = 3 p = 3/3 C pt = 6 p = 6/3 C pt = 6 p = 6/3 Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter NAND n NOR n Tristate / mux 2 4 6 8 2n XOR, XNOR 4 6 8 Parasitic delay of common gates In multiples of p inv ( 1) Examples A B
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