EEL6323S12-HLec05-LogicalEffort-4spp

# • measure from delay vs fanout plots • or

This preview shows pages 3–5. Sign up to view the full content.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: • Measure from delay vs. fanout plots • Or estimate by counting transistor widths A Y A B Y A B Y 1 2 1 1 2 2 2 2 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Logical Effort • Use delay versus fanout curves – Slope of lines is the logical effort Electrical Effort: h = C out / C in Normalized Delay: d Inverter 2-input NAND g = 1 p = 1 d = h + 1 g = 4/3 p = 2 d = (4/3)h + 2 Effort Delay: f Parasitic Delay: p 1 2 3 4 5 1 2 3 4 5 6 d = f + p = gh + p Catalog of Gates Gate type Number of inputs 1 2 3 4 n Inverter NAND (n+2)/3 NOR (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 • Logical effort of common gates Electrical Effort • Electrical Effort: h – Ratio of output to input capacitance – Sometimes called fanout d = f + p = gh + p 4 Parasitic Delay • Parasitic Delay: p – Independent of logic gate size and load capacitance – Defined by Cdb of the output node (internal Cdb neglected) – Assume Cdb is linearly proportional to transistor widths d = f + p = gh + p ( ) p gh C R C R C R C C C R C R C R d inv inv pt t inv inv in out inv inv t t inv inv abs + = ⋅ + Ο Ο Π Ξ Μ Μ Ν Λ ⋅ = τ κ κ Inverter Parasitic Delay • Define the normalized inverter parasitic delay ( p inv ) – p inv is the ratio of unit diffusion capacitance and unit gate capacitance...
View Full Document

{[ snackBarMessage ]}

### Page3 / 5

• Measure from delay vs fanout plots • Or estimate by...

This preview shows document pages 3 - 5. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online