EEE6323S12-HLec04-DCTransient-4spp

# T cdf falling contamination delay minimum time from

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t cdf : falling contamination delay Minimum time from input 50% crossing to falling output crossing V DD /2 t cd : average contamination delay t pd = (t cdr + t cdf )/2 t r : rise time (From output crossing 0.2 V DD to 0.8 V DD t f : fall time (From output crossing 0.8 V DD to 0.2 V DD ) tmin tmax t pHL t pLH t t V in V out 50% 50% t r 20% 80% t f

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4 Delay Estimation SPICE simulator solves the equations numerically Solving differential equations by hand is too hard We would like to be able to easily estimate delay Use RC delay models to estimate delay Characterize transistors by finding their effective R Depends on average current as gate switches (V) 0.0 0.5 1.0 1.5 2.0 t(s) 0.0 200p 400p 600p 800p 1n tpdf = 66ps tpdr = 83ps V in V out The step response usually looks like a 1st order RC response with a decaying exponential. RC Delay Approximation Use equivalent circuits for MOS transistors Capacitance proportional to width Resistance inversely proportional to width k g s d g s d kC kC kC R/k k g s d g s d kC kC kC 2R/k Capacitance n+ n+ p-type body L t ox SiO 2 gate oxide ε ox = 3.9 ε 0 On Resistance 250nm process n> R eqn = R n Wn R eqp = R p Wp
5 Inverter Delay Estimation Estimate delay of FO1 inverter C C R 2C 2C R 2 1 A Y C 2C C 2C C 2C R Y 2 1 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). Assume Rp=2Rn.

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