The complexity of the algorithm is o n 2 other

The complexity of the algorithm is O( n
2
)
Other algorithms (such as Deferred Merge Embedding)
require more programming effort but the problem
complexity is better, e.g., O( n )

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing and Power Analysis
Chapter 3: Timing and Power Analysis 217
Chapter 3: Timing and Power Analysis 218
Timing Analysis
Timing Analysis
Dynamic and Static Timing Analysis (DTA and STA)
Method
Needs Test Vectors
Risk
Static Dynamic
Path Analysis Simulation
No Yes
False alarms Missed alarms
CPU Run time
Memory Usage
Coverage Pattern dependent Pattern independent
Days / Weeks Hours
Heavy Light - Moderate
Min-Max Analysis Yes Discontinued
Couple with Synthesis Yes Not feasible

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing and Power Analysis
Chapter 3: Timing and Power Analysis 219
False Paths in STA
STA ignores paths that are not responsible for delay (false
path) - How to determine if a path is a false path?
If false paths are not ignored, delay can be overestimated
(this is acceptable but not desirable)
Controlling and Non-controlling (sensitizing) values
0
0
1
Controlling value of AND
Controlled value of AND
1
1
Controlling value of OR
Controlled value of OR
Non-Controlling value of AND
0
Non-Controlling value of OR
Chapter 3: Timing and Power Analysis 220
Statically Sensitized Paths
•
A path is statically sensitized if there exists an input vector such
that if all the side inputs to the path are set to non -controlling
values, then signal propagates through the path
Combinational
Logic
Memory
Elements
Clock
Primary
Inputs
Primary
Outputs
N1
N2
N3
N4
N6
1
1
0

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing and Power Analysis
Chapter 3: Timing and Power Analysis 221
– Path in0-w2-w3-out is NOT statically-
sensitizable path (false path)
– Similarly, path in1-w2-w3-out is also
false path
output out;
input in0, in1, in2;
nor (w1, in0, in1);
and (w2, in0, in1);
or (w3, w2, in2);
and (out, w1, w3);
1
0
0
Example
T1 T2 Tdelta
Name
0 10 20 30 40
Default
in0
in1
in2
w1
w2
w3
out
Chapter 3: Timing and Power Analysis 222
T1 T2 Tdelta
Name S
0 40 80 120
Default
in0
in1
in2
w5
w6
out
w5 does not change by in 1, which leads
to in 1 -w1-w3-w5-out is false path
output w5, w6, out;
input in0, in1, in2;
wire w1, w2, w3, w4;
and (w1, in0, in1);
and (w2, in0, in2);
and (w3, in2, w1);
not (w4, w2);
and (w5, w4, w3);
and (w6, in1, w2);
or (out, w6, w5);
Another example

EE271 @ Thuy T. Le SJSU - EE
Chapter 3: Timing and Power Analysis
Chapter 3: Timing and Power Analysis 223
Multiplexer
Delay =15
Delay = 30
Delay = 15
Delay = 30
Sel
Data_in Data_out
False path
Multiplexer
Another example
A topological path is said to be a false path if it is not a
functional path under the action of the primary inputs
If the path CANNOT be statically sensitized (false path)
then it should be removed from the delay calculations
Chapter 3: Timing and Power Analysis 224
•
But checking for false paths (as we did), delay estimation still
has problems because:
• The same signal can have a controlling value at one time and a non-
controlling value at another time ( dynamically sensitized ) and this
leads to underestimation of delay ( not acceptable )
Example:
output out;
input in0, in1, in2;
nor #1(w1, in0, in1);
and #1(w2, in0, in1);
or #1(w3, w2, in2);
and #1(out, w1, w3);
T1 0 T2 Tdelta