The complexity of the algorithm is O n 2 Other algorithms such as Deferred

The complexity of the algorithm is o n 2 other

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The complexity of the algorithm is O(n2)Other algorithms (such as Deferred Merge Embedding) require more programming effort but the problem complexity is better, e.g., O(n)
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EE271 @ Thuy T. LeSJSU - EEChapter 3: Timing and Power AnalysisChapter 3: Timing and Power Analysis217Chapter 3: Timing and Power Analysis218Timing AnalysisTiming AnalysisDynamic and Static Timing Analysis (DTA and STA)MethodNeeds Test VectorsRiskStaticDynamicPath AnalysisSimulationNoYesFalse alarmsMissed alarmsCPU Run timeMemory UsageCoveragePattern dependentPattern independentDays / WeeksHoursHeavyLight - ModerateMin-Max AnalysisYesDiscontinuedCouple with SynthesisYesNot feasible
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EE271 @ Thuy T. LeSJSU - EEChapter 3: Timing and Power AnalysisChapter 3: Timing and Power Analysis219False Paths in STASTA ignores paths that are not responsible for delay (false path) - How to determine if a path is a false path?If false paths are not ignored, delay can be overestimated (this is acceptable but not desirable)Controlling and Non-controlling (sensitizing) values001Controlling value of ANDControlled value of AND11Controlling value of ORControlled value of ORNon-Controlling value of AND0Non-Controlling value of ORChapter 3: Timing and Power Analysis220Statically Sensitized Paths A path is statically sensitized if there exists an input vector such that if all the side inputs to the path are set to non-controlling values, then signal propagates through the pathCombinationalLogicMemoryElementsClockPrimaryInputsPrimaryOutputsN1N2N3N4N6110
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EE271 @ Thuy T. LeSJSU - EEChapter 3: Timing and Power AnalysisChapter 3: Timing and Power Analysis221– Path in0-w2-w3-outis NOT statically-sensitizable path (false path)Similarly, path in1-w2-w3-outis also false pathoutput out;input in0, in1, in2;nor (w1, in0, in1);and (w2, in0, in1);or (w3, w2, in2); and (out, w1, w3);100ExampleT1 T2 Tdelta Name010203040Defaultin0in1in2w1w2w3outChapter 3: Timing and Power Analysis222T1 T2 Tdelta NameS04080120Defaultin0in1in2w5w6outw5does not change by in1, which leads to in1-w1-w3-w5-outis false pathoutput w5, w6, out;input in0, in1, in2;wire w1, w2, w3, w4;and (w1, in0, in1);and (w2, in0, in2);and (w3, in2, w1);not (w4, w2);and (w5, w4, w3);and (w6, in1, w2);or (out, w6, w5);Another example
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EE271 @ Thuy T. LeSJSU - EEChapter 3: Timing and Power AnalysisChapter 3: Timing and Power Analysis223MultiplexerDelay =15Delay = 30Delay = 15Delay = 30SelData_inData_outFalse pathMultiplexerAnother exampleA topological path is said to be afalse path if it is not a functional pathunder the action of the primary inputsIf the path CANNOT be statically sensitized (false path) then it should be removedfrom the delay calculationsChapter 3: Timing and Power Analysis224But checking for false paths (as we did), delay estimation stillhas problems because:The same signal can have a controllingvalue at one time and a non-controllingvalue at another time (dynamically sensitized) and this leads to underestimation of delay (not acceptable)Example:output out;input in0, in1, in2;nor #1(w1, in0, in1);and #1(w2, in0, in1);or #1(w3, w2, in2); and #1(out, w1, w3);T1 0 T2 Tdelta
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  • Spring '08
  • ThuyLe
  • Clock signal, Logic gate, power analysis

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