# Exercise repeat the above example if 1532 nand gate

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Exercise Repeat the above example if . 15.3.2 NAND Gate The developments in Section 15.3.1 for the NOR gate can readily be extended to create a NAND gate. Since an NAND operation, , produces a zero output if both inputs are high, we con-

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 808 (1) 808 Chap. 15 Digital CMOS Circuits struct the NMOS section as shown in Fig. 15.35(a), where or blocks the path from M M 1 A B 2 out V V DD M M 3 4 A B out V V DD M M 3 4 M M 1 A 2 out V B (a) (b) (c) Figure 15.35 (a) NMOS section of a NAND gate, (b) PMOS section of a NAND gate, (c) complete CMOS NAND gate. to ground unless both and remain high. The PMOS section, on other hand, must pull to if at least one of the inputs is low, and is thus realized as shown in Fig. 15.35(b). Figure 15.35(c) depicts the overall NAND gate. This circuit, too, consumes zero static power. In contrast to the NOR gate, the NAND gate places NMOS devices in series, thus suffering less severely from speed limitation of PMOS transistors. The following example illustrates this point. Example 15.29 Design a three-input NAND gate and determine the relative widths of the transistors for equal rise and fall times. Assume and equal channel lengths. Solution Figure 15.36 shows the realization of the gate. With three NMOS transistors in series, we select V DD M M M M out V M 1 2 3 M A B C 4 5 6 Figure 15.36 a width of for - so that the total series resistance is equivalent to one device having a width of . Each PMOS device must therefore have a width of . Consequently, the capaci- tance seen at each input is roughly equal to , about less than that of the NOR gate in Example 15.28. Exercise Repeat the above example if .
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 809 (1) Sec. 15.4 Chapter Summary 809 In CMOS logic, the PMOS and NMOS sectios are called “dual” of each other. In fact, given one section, we can construct the other according to the following rule: convert each series branch to parallel branches and vice versa. Example 15.30 Determine the PMOS dual of the circuit shown in Fig. 15.37(a) and determine the logical func- tion performed by the overall CMOS realization. V DD M M out V M M M A B C 1 2 3 out V B M V DD M M A B M M M M A B C 1 2 3 out V A C C 4 5 6 4 5 6 (a) (b) (c) Figure 15.37 Solution Here, and are placed in series (to perform a NAND operation) and the combination appears in parallel with (to implement a NOR function). The PMOS dual therefore consists of a parallel combination of two transistors, and a third transistor in series with this combination [Fig. 15.37(b)]. Figure 15.37(c) depicts the overall gate, which performs the logical function . Exercise Suppose is accidentally omitted. Study the behavior of the gate. 15.4 Chapter Summary Digital CMOS circuits account for more than 80% of the semiconductor market.

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