multiple upsets . The effects of MBU are typically allevi-ated by a combination of error-correcting codes that work on aword-by-word basis (see Section VI) and layout rules that pre-vent physically adjacent bits from belonging to the same wordof memory. Still, single-word multiple-bit upsets (SMUs) canoccur and pose a substantial threat to system integrity .MBUs have been observed in on-orbit spacecraft data , .As advanced technologies pack ever more bits into small areas,MBU may become more prevalent.D. Functional InterruptsSingle-event functional interrupts (SEFIs) are a complexfailure mode whereby an ion strike triggers an IC test mode,a reset mode, or some other mode that causes the IC totemporarily lose functionality . As devices become increas-ingly complex, they may be more likely to exhibit SEFIs. Forexample, synchronous DRAMs are very complicated ICs thatincorporate built-in self-test (BIST) modes and self-repairingboot sequences that remap nonfunctional bits in the memorywith redundant bits on the chip. An ion strike to a SDRAMwith such circuits may initiate a BIST mode, cause a chip resetto occur, or throw the IC into an idle state . These eventscan have serious consequences on system operation, sometimesrequiring device reset to clear the condition .V. SEE MECHANISMS INLOGICThe quantification of SEU effects in combinational logic cir-cuits (e.g., core logic of a microprocessor or microcontroller) isquite different than in memories. Whether or not an erroneousdata signal caused by a single-event ion strike is captured by astorage element (latch or register) depends on the existence ofactive paths from the struck node to latches, the arrival time ofthe erroneous signal at the latches, and the erroneous pulse timeprofile at the latch input. Even if the erroneous signal is cap-tured (stored) by one or more latches, there is still no guaranteethat it will propagate to the output. The erroneous informationmay be blocked by superseding logic during the following clockcycles—i.e., the corrupted latch may become a “don’t care”member of a subsequent state of the logic. In core logic, theconcepts of “faults” and “errors” are distinct from memory cir-cuits and require precise definition.A. Combinational Soft FaultsIn a logic circuit, charge collection due to a single-event strikeon a particular node will generate a low-to-high or high-to-lowvoltage transition or a transient noise pulse. If this pulse is largerthan the input noise margin of a subsequent gate, it will com-pete with the legitimate digital pulses propagating through thecircuit. The ability of the noise pulse to propagate depends notonly on its magnitude, but also on the active logic paths fromthe node existing at that instant in time. An example of this isshown in Fig. 7 .