The effects of mbu are typically allevi ated by a

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multiple upsets [79]. The effects of MBU are typically allevi- ated by a combination of error-correcting codes that work on a word-by-word basis (see Section VI) and layout rules that pre- vent physically adjacent bits from belonging to the same word of memory. Still, single-word multiple-bit upsets (SMUs) can occur and pose a substantial threat to system integrity [80]. MBUs have been observed in on-orbit spacecraft data [81], [82]. As advanced technologies pack ever more bits into small areas, MBU may become more prevalent. D. Functional Interrupts Single-event functional interrupts (SEFIs) are a complex failure mode whereby an ion strike triggers an IC test mode, a reset mode, or some other mode that causes the IC to temporarily lose functionality [83]. As devices become increas- ingly complex, they may be more likely to exhibit SEFIs. For example, synchronous DRAMs are very complicated ICs that incorporate built-in self-test (BIST) modes and self-repairing boot sequences that remap nonfunctional bits in the memory with redundant bits on the chip. An ion strike to a SDRAM with such circuits may initiate a BIST mode, cause a chip reset to occur, or throw the IC into an idle state [84]. These events can have serious consequences on system operation, sometimes requiring device reset to clear the condition [85]. V. SEE M ECHANISMS IN L OGIC The quantification of SEU effects in combinational logic cir- cuits (e.g., core logic of a microprocessor or microcontroller) is quite different than in memories. Whether or not an erroneous data signal caused by a single-event ion strike is captured by a storage element (latch or register) depends on the existence of active paths from the struck node to latches, the arrival time of the erroneous signal at the latches, and the erroneous pulse time profile at the latch input. Even if the erroneous signal is cap- tured (stored) by one or more latches, there is still no guarantee that it will propagate to the output. The erroneous information may be blocked by superseding logic during the following clock cycles—i.e., the corrupted latch may become a “don’t care” member of a subsequent state of the logic. In core logic, the concepts of “faults” and “errors” are distinct from memory cir- cuits and require precise definition. A. Combinational Soft Faults In a logic circuit, charge collection due to a single-event strike on a particular node will generate a low-to-high or high-to-low voltage transition or a transient noise pulse. If this pulse is larger than the input noise margin of a subsequent gate, it will com- pete with the legitimate digital pulses propagating through the circuit. The ability of the noise pulse to propagate depends not only on its magnitude, but also on the active logic paths from the node existing at that instant in time. An example of this is shown in Fig. 7 [86].

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