If the boot ROM is bypassed by Code Composer Studio during the development

If the boot rom is bypassed by code composer studio

This preview shows page 83 - 86 out of 200 pages.

If the boot ROM is bypassed by Code Composer Studio during the development process, then ADCREFSEL and ADCOFFTRIM must be initialized by the application. For working examples, see the ADC initialization in the C2833x, C2823x C/C++ Header Files and Peripheral Examples (literature number SPRC530 ). Methods for calling the ADC_cal() routine from an application are described in TMS320x2833x, F2823x Analog-to-Digital Converter (ADC) Module Reference Guide (literature number SPRU812 ). NOTE FAILURE TO INITIALIZE THESE REGISTERS WILL CAUSE THE ADC TO FUNCTION OUT OF SPECIFICATION. If the system is reset or the ADC module is reset using Bit 14 (RESET) from the ADC Control Register 1, the routine must be repeated. Copyright © 2007–2010, Texas Instruments Incorporated Peripherals 83 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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( ) CLKSRG CLKG = 1+ CLKGDV TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 4.8 Multichannel Buffered Serial Port (McBSP) Module The McBSP module has the following features: Compatible to McBSP in TMS320C54x™/ TMS320C55x™ DSP devices Full-duplex communication Double-buffered data registers that allow a continuous data stream Independent framing and clocking for receive and transmit External shift clock generation or an internal programmable frequency shift clock A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits 8-bit data transfers with LSB or MSB first Programmable polarity for both frame synchronization and data clocks Highly programmable internal clock and frame generation Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices Works with SPI-compatible devices The following application interfaces can be supported on the McBSP: T1/E1 framers IOM-2 compliant devices AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.) IIS-compliant devices SPI McBSP clock rate, where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit. NOTE See Section 6 for maximum I/O pin toggling speed. 84 Peripherals Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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16 McBSP Receive Interrupt Select Logic MDXx MDRx Expand Logic DRR1 Receive Buffer RX Interrupt DRR2 Receive Buffer RBR1 Register RBR2 Register MCLKXx MFSXx MCLKRx MFSRx 16 Compand Logic DXR2 Transmit Buffer RSR1 XSR2 XSR1 Peripheral Read Bus 16 16 16 16 16 RSR2 DXR1 Transmit Buffer LSPCLK MRINT To CPU RX Interrupt Logic McBSP Transmit Interrupt Select Logic TX Interrupt MXINT To CPU TX Interrupt Logic 16 16 16 Bridge DMA Bus Peripheral Bus Peripheral Write Bus CPU CPU CPU TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 Figure 4-11 shows the block diagram of the McBSP module.
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