Sequencing unit that dispatches tasks to each one

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Sequencing unit that dispatches tasks to each one Shared register file that resolves RAW/WAR/WAW Address Resolution Buffer: resolves memory dependences Publications, theses, tools, contact information
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Niagara Case Study Targeted application: web servers Memory intensive (many cache misses) ILP limited by memory behavior TLP: Lots of available threads (one per client) Design goal: maximize throughput (/watt) Results: Pack many cores on die (8) Keep cores simple to fit 8 on a die, share FPU Use multithreading to cover pipeline stalls Modest frequency target (1.2 GHz)
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Niagara Block Diagram [Source: J. Laudon] 8 in-order cores, 4 threads each 4 L2 banks, 4 DDR2 memory controllers
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Ultrasparc T1 Die Photo [Source: J. Laudon]
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Niagara Pipeline [Source: J. Laudon] Shallow 6-stage pipeline Fine-grained multithreading
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Power Consumption [Source: J. Laudon]
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Thermal Profile Low operating temp No hot spots Improved reliability No need for exotic cooling
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T2000 System Power 271W running SpecJBB2000 Processor is only 25% of total DRAM & I/O next, then conversion losses
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Niagara Summary Example of application-specific system optimization Exploit application behavior (e.g. TLP, cache misses, low ILP) Build very efficient solution Downsides Loss of general-purpose suitability E.g. poorly suited for software development (parallel make, gcc) Very poor FP performance (fixed in Niagara 2)
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Lecture Summary Thread-level parallelism Synchronization Multiprocessors Explicit multithreading Implicit multithreading: Multiscalar Niagara case study
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  • Fall '09
  • PROFGURISOHI
  • Central processing unit, CPU cache, thread-level parallelism

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