2 data in typ column is at 50v 25c unless otherwise

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dsPIC33EVXXXGM00X/10X FAMILY DS70005144E-page 388 2013-2016 Microchip Technology Inc. TABLE 30-46: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Standard Operating Conditions: 4.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T A +85°C for Industrial -40°C T A +125°C for Extended Param No. Symbol Characteristic ( 4 ) Min. ( 1 ) Max. Units Conditions IM10 T LO : SCL Clock Low Time 100 kHz mode T CY /2 (BRG + 2) s 400 kHz mode T CY /2 (BRG + 2) s 1 MHz mode ( 2 ) T CY /2 (BRG + 2) s IM11 T HI : SCL Clock High Time 100 kHz mode T CY /2 (BRG + 2) s 400 kHz mode T CY /2 (BRG + 2) s 1 MHz mode ( 2 ) T CY /2 (BRG + 2) s IM20 T F : SCL SDAx and SCLx Fall Time 100 kHz mode 300 ns C B is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 C B 300 ns 1 MHz mode ( 2 ) 100 ns IM21 T R : SCL SDAx and SCLx Rise Time 100 kHz mode 1000 ns C B is specified to be from 10 to 400 pF 400 kHz mode 20 + 0.1 C B 300 ns 1 MHz mode ( 2 ) 300 ns IM25 T SU : DAT Data Input Setup Time 100 kHz mode 250 ns 400 kHz mode 100 ns 1 MHz mode ( 2 ) 40 ns IM26 T HD : DAT Data Input Hold Time 100 kHz mode 0 s 400 kHz mode 0 0.9 s 1 MHz mode ( 2 ) 0.2 s IM30 T SU : STA Start Condition Setup Time 100 kHz mode T CY /2 (BRG + 2) s Only relevant for Repeated Start condition 400 kHz mode T CY /2 (BRG + 2) s 1 MHz mode ( 2 ) T CY /2 (BRG + 2) s IM31 T HD : STA Start Condition Hold Time 100 kHz mode T CY /2 (BRG + 2) s After this period, the first clock pulse is generated 400 kHz mode T CY /2 (BRG +2) s 1 MHz mode ( 2 ) T CY /2 (BRG + 2) s IM33 T SU : STO Stop Condition Setup Time 100 kHz mode T CY /2 (BRG + 2) s 400 kHz mode T CY /2 (BRG + 2) s 1 MHz mode ( 2 ) T CY /2 (BRG + 2) s IM34 T HD : STO Stop Condition Hold Time 100 kHz mode T CY /2 (BRG + 2) s 400 kHz mode T CY /2 (BRG + 2) s 1 MHz mode ( 2 ) T CY /2 (BRG + 2) s IM40 T AA : SCL Output Valid From Clock 100 kHz mode 3500 ns 400 kHz mode 1000 ns 1 MHz mode ( 2 ) 400 ns IM45 T BF : SDA Bus Free Time 100 kHz mode 4.7 s Time the bus must be free before a new transmission can start 400 kHz mode 1.3 s 1 MHz mode ( 2 ) 0.5 s IM50 C B Bus Capacitive Loading 400 pF IM51 T PGD Pulse Gobbler Delay 65 390 ns See Note 3 Note 1: BRG is the value of the I 2 C Baud Rate Generator. Refer to “Inter-Integrated Circuit™ (I 2 C™)” (DS70000195) in the “dsPIC33/PIC24 Family Reference Manual”. Please see the Microchip web site for the latest
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