Physical register file merged arf rrf mips r10000

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Physical Register File: merged ARF & RRF (MIPS R10000 , Pentium 4, Alpha 21264, Power 4-7, Nehalem, Sandybridge, Bulldozer, Bobcat) No copy; simpler datapath (operand always in PRF)
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ARF vs. PRF We showed that PRF is better [ISLPED 07] – everyone now agrees! P6 thru Core 2 Duo (Merom): ARF Pentium4/Nehalem/Sandybridge, AMD Bulldozer & Bobcat: PRF RAT ROB RS PRF Bypass ALU Physical Register File - style
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Misprediction Recovery Branch mispredicts, exceptions: must reclaim allocated resources Load queue, store queue/color, branch color, ROB entry, rename register Can reclaim implicitly Tag broadcast: all entities match & release Too expensive for physical register file (PRF) Or reclaim explicitly Walk through ROB which contains pointers Follow pointers to release resources Also, recover rename mappings Read previous mappings (pending release) and repair map table Valid PC Dest PR Pre v PR Src 1 Src 2 Imm/ target Issue d Execute d Excepti on T/NT Pred 1 x400 C P13 P17 P25 n/a X80 Y Y N 1 X400 8 P14 P22 P31 P5 Y N N 1 X400 4 x4020 NT
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Rename Table Implementation MAP checkpointing Performance optimization Recovery from branches, exceptions Checkpoint granularity Every instruction Every branch, play back ROB to get to exception boundary RAM vs CAM Map Table
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RAM Map Table Just a lookup table Checkpoint size: n (# arch reg) x log 2 (phys reg)
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CAM Map Table CAM search for mappings # rows == number of physical registers Checkpoint only the valid bit column Used in Alpha 21264
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Summary Register dependences True dependences Antidependences Output dependences Register Renaming Tomasulo’s Algorithm Reservation Station Implementation Reorder Buffer Implementation Register File Implementation History file Future file Physical register file Rename Table Implementation
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  • Fall '09
  • PROFGURISOHI
  • Processor register, Register renaming, Tomasulo algorithm, Register file, Out-of-order execution

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