Programming fpgas example cont bitfile is just a

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Programming FPGAs Example, Cont: Bitfile is just a sequence of bits based on order of shift register FF 2x1 1 1 0 1 0 0 1 1 0 FF 2x1 1 0 1 1 0 1 0 0 1 After programming During programming
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01-Oct-19 47 Programming FPGAs Example, Cont: Bitfile is just a sequence of bits based on order of shift register FF 2x1 1 0 1 1 0 1 0 0 1 FF 2x1 1 0 1 1 0 1 0 0 1 After programming During programming CLB is programmed to implement full adder! Easily extended to program entire FPGA Programming FPGAs Problem: Reconfiguring FPGA is slow Shifting in 1 bit at a time not efficient Bitfiles can be greater than 1 MB Eliminates one of the main advantages of RC Partial reconfiguration With shift registers, entire FPGA has to be reconfigured Solutions? Virtex II allows columns to be reconfigured Virtex IV allows custom regions to be reconfigured Requires a lot of user effort Better tools needed
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01-Oct-19 48 FPGA Architecture Tradeoffs LUTs with many inputs can implement large circuits efficiently Why not just use LUTs with many inputs? High flexibility in routing resources improves routability Why not just allow all possible connections? Answer: architectural tradeoffs Anytime one component is increased/improved, there is less area for other components Larger LUTs => less total LUTs, less routing resources More Block RAM => less LUTs, less DSPs More DSPs => less LUTs, less Block RAM Etc. FPGA Architecture Tradeoffs Example: Determine best LUTs for following circuit Choices 4-input, 2-output LUT (delay = 2 ns) 5-input, 2-output LUT (delay = 3 ns) Assume each SRAM cell is 6 transistors 4-input LUT = 6 * 2 4 * 2 = 192 transistors 5-input LUT = 6 * 2 5 * 2 = 384 transistors
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01-Oct-19 49 FPGA Architecture Tradeoffs Example: Determine best LUTs for following circuit Choices 4-input, 2-output LUT (delay = 2 ns) 5-input, 2-output LUT (delay = 3 ns) Assume each SRAM cell is 6 transistors 4-input LUT = 6 * 2 4 * 2 = 192 transistors 5-input LUT = 6 * 2 5 * 2 = 384 transistors 5-input LUT Propagation delay = 6 ns Total transistors = 384 * 2 = 768 FPGA Architecture Tradeoffs Example: Determine best LUTs for following circuit Choices 4-input, 2-output LUT (delay = 2 ns) 5-input, 2-output LUT (delay = 3 ns) Assume each SRAM cell is 6 transistors 4-input LUT = 6 * 2 4 * 2 = 192 transistors 5-input LUT = 6 * 2 5 * 2 = 384 transistors 4-input LUT Propagation delay = 4 ns Total transistors = 192 * 2 = 384 4-input LUTs are 1.5x faster and use 1/2 the area
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01-Oct-19 50 FPGA Architecture Tradeoffs Example 2 Determine best LUTs for following circuit Choices 4-input, 2-output LUT (delay = 2 ns) 5-input, 2-output LUT (delay = 3 ns) Assume each SRAM cell is 6 transistors 4-input LUT = 6 * 2 4 * 2 = 192 transistors 5-input LUT = 6 * 2 5 * 2 = 384 transistors FPGA Architecture Tradeoffs Example 2 Determine best LUTs for following circuit Choices 4-input, 2-output LUT (delay = 2 ns) 5-input, 2-output LUT (delay = 3 ns) Assume each SRAM cell is 6 transistors 4-input LUT = 6 * 2 4 * 2 = 192 transistors 5-input LUT = 6 * 2 5 * 2 = 384 transistors 5-input LUT Propagation delay = 3 ns Total transistors = 384
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01-Oct-19 51 FPGA Architecture Tradeoffs Example 2 Determine best LUTs for following circuit Choices 4-input, 2-output LUT (delay = 2 ns) 5-input, 2-output LUT (delay = 3 ns) Assume each SRAM cell is 6 transistors
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