ESC201A-Endsem_paper 2015 Solution.pdf

M f m f now the final design becomes 30 marks for

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m F m F Now the final design becomes, [ 3.0 Marks for correct logic circuit below] 5) Frequency=1kHz Time period=1ms Since, 1 2 1 0 I I I , output=5V for 3ms, and since 0 3 I , output=0V for 1ms after this is repeated every 4ms, i.e cycle corresponding to binary counter 00,01,10,11. Output waveform Y for 8ms is given as, [ 2.0 Marks for correct waveform]
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Given RC = 1ms. Let 2 1 , V V be max, min capacitor voltages in steady state. We have, [ 3.0 Marks each for correct V 1 , V2 i.e. total 6.0 Marks if both are correct] V e e e e V V V e e V e V e V e e V V e V V e V RC RC RC RC RC RC RC RC RC RC RC RC 78 . 1 1 1 5 84 . 4 1 1 5 1 5 5 5 5 5 5 3 3 3 3 3 3 3 3 3 3 3 3 10 1 10 4 10 3 10 1 1 2 10 4 10 3 1 10 4 1 10 3 1 10 3 10 1 1 2 10 1 1 1 10 3 2 6) Response is initially increasing at 40dB/decade. Subsequently slope decreases by 20dB/decade 4 times. Therefore, frequency response can be seen to be given as, [ 3.0 Marks for correct form of expression with correct values of corner frequencies] 2 4 2 2 3 2 2 2 2 2 1 2 4 2 1 1 1 1 ) ( K H From figure,
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s Rad s Rad s Rad s Rad / 100 / 10 / 1 / 1 . 0
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