4 429 are there any replacement policies for the

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4. [ ,429 ] Are there any replacement policies for the fully associative cache that would outperform the direct-mapped cache? (Ignore the policy of “do what a direct-mapped cache would do”);
5. [379, 401] What is a write-through cache? Is it faster/slower than a write-back cache with respect to the time it takes for writing.
III. Problem 3 (25 points) [Q3.1, Q2.4] Use the following code fragment whereby the initial value of R3 is R2+396: Loop: LW R1, 0(R2) ADDI R1, R1, #1 SW 0(R2), R1 ADDI R2, R2, #4 SUB R4, R3, R2 BNEZ R4, Loop Throughout this exercise use the MIPS integer pipeline and assume all memory accesses are cache hits. Show the timing of this instruction sequence for the MIPS pipeline without any forwarding or bypassing hardware but assuming a register read and a write in the same clock cycle “forwards” through the register file. Use a pipeline-timing chart. Assume that the branch is handled by flushing the pipeline. If all memory references hit in the cache, how many cycles does this loop take to execute? 18 19 20 21 22 M W X M W X M W M W X M W X M W X M W
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Computer Architecture, Final Exam 15 December 2004 cycles 16-17: bnz computes the next PC in MEM implying that the lw cannot be fetched until after cycle 17 (note the fetch in cycle 15 is also wasted) In this figure we have assumed the version of MIPS, which resolves branches in MEM. The second iteration begins 17 clocks after the first iteration and the last iteration takes 18 cycles to complete. This implies that iteration i (where iterations are numbered from 0 to 98) begins on clock cycle 1+17xi. As the loop executes 99 times the loop executes in a total of (98x17)+18=1684 clocks. Show the timing of this instruction sequence in the MIPS pipeline with normal forwarding and bypassing hardware. Use a pipeline timing chart. Assume that the branch is handled by predicting it as not taken. If all memory references hit in the cache, how many cycles does this loop take to execute? Clock Cycle Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lw

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