681 Power Management and Supervisory Circuit Solutions Table 6 10 lists the

681 power management and supervisory circuit

This preview shows page 127 - 130 out of 200 pages.

6.8.1 Power Management and Supervisory Circuit Solutions Table 6-10 lists the power management and supervisory circuit solutions for 2833x/2823x devices. LDO selection depends on the total power consumed in the end application. Go to and click on Power Management for a complete list of TI power ICs or select the Power Management Selection Guide link for specific power reference designs. Table 6-10. Power Management and Supervisory Circuit Solutions SUPPLIER TYPE PART DESCRIPTION Texas Instruments LDO TPS767D301 Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS) Texas Instruments LDO TPS70202 Dual 500/250-mA LDO with SVS Texas Instruments LDO TPS766xx 250-mA LDO with PG Texas Instruments SVS TPS3808 Open Drain SVS with programmable delay Texas Instruments SVS TPS3803 Low-cost Open-drain SVS with 5 m S delay Texas Instruments LDO TPS799xx 200-mA LDO in WCSP package Texas Instruments LDO TPS736xx 400-mA LDO with 40 mV of V DO Texas Instruments DC/DC TPS62110 High V in 1.2-A dc/dc converter in 4x4 QFN package Texas Instruments DC/DC TPS6230x 500-mA converter in WCSP package Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 127 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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t w(RSL1) t h(boot-mode) (B) V DDIO , V DD3VFL V DDA2 , V DDAIO (3.3 V) XCLKIN X1/X2 XRS Boot-Mode Pins V DD , V DD1A18, V DD2A18 (1.9 V/1.8 V) XCLKOUT I/O Pins (C) User-Code Dependent User-Code Dependent Boot-ROM Execution Starts Peripheral/GPIO Function Based on Boot Code GPIO Pins as Input OSCCLK/16 (A) GPIO Pins as Input (State Depends on Internal PU/PD) t OSCST User-Code Dependent Address/Data/ Control (Internal) Address/Data Valid. Internal Boot-ROM Code Execution Phase User-Code Execution Phase t d(EX) OSCCLK/8 TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 A. Upon power up, SYSCLKOUT is OSCCLK/4. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/16 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2. Because the XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/8 during this phase. B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. C. See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up. Figure 6-6. Power-on Reset 128 Electrical Specifications Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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t h(boot-mode) (A) t w(RSL2) XCLKIN X1/X2 XRS Boot-Mode Pins XCLKOUT I/O Pins Address/Data/ Control (Internal)
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