231 Declaring and initializing fixed size array Verilog requires that the low

231 declaring and initializing fixed size array

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2.3.1 Declaring and initializing fixed-size array Verilog requires that the low and high array limits must be given in the declaration. Almost all arrays use a low index of 0, so SystemVerilog lets you use the shortcut of just giving the array size, similar to C: Example 2-4 Declaring fixed-size arrays int lo_hi[0:15]; // 16 ints [0]..[15] int c_style[16]; // 16 ints [0]..[15] You can create multidimensional fixed-size arrays by specifying the dimensions after the variable name. This is an unpacked array; packed arrays are shown later. The following creates several two-dimensional arrays of inte- gers, 8 entries by 4, and sets the last entry to 1. Multidimensional arrays were introduced in Verilog-2001, but the compact declarations are new. Example 2-5 Declaring and using multidimensional arrays int array2 [0:7][0:3]; // Verbose declaration int array3 [8][4]; // Compact declaration array2[7][3] = 1; // Set last array element
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SystemVerilog for Verification 30 SystemVerilog stores each element on a longword (32-bit) boundary. So a byte , shortint , and int are all stored in a single longword, while a long- int is stored in two longwords. (Simulators frequently store four-state types such as logic and integer in two or more longwords.) Example 2-6 Unpacked array declarations bit [7:0] b_unpacked[3]; // Unpacked The unpacked array of bytes, b_unpacked, is stored in three longwords. Figure 2-1 Unpacked array storage 2.3.2 The array literal You can initialize an array using an array literal that is an apostrophe and curly braces. 1 You can set some or all elements at once. You can replicate val- ues by putting a count before the curly braces. Example 2-7 Initializing an array int ascend[4] = ’{0,1,2,3}; // Initialize 4 elements int decend[5]; int md[2][3] = ’{’{0,1,2}, ’{3,4,5}}; descend = ’{4,3,2,1,0}; // Set 5 elements descend[0:2] = ’{5,6,7}; // Set first 3 elements ascend = ’{4{8}}; // Four values of 8 2.3.3 Basic array operations — for and foreach The most common way to manipulate an array is with a for or foreach loop. In Example 2-8, the variable i is declared local to the for loop. The SystemVerilog function $size returns the size of the array. In the foreach statement, you specify the array name and an index in square brackets, and SystemVerilog automatically steps through all the elements of the array. The index variable is local to the loop. 1. VCS X-2005.06 follows the original Accellera standard for array literals and uses just the curly braces with no leading apostrophe. VCS will change to the IEEE standard in an upcoming release. b_array[1] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Unused space b_array[2] b_array[0]
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Chapter 2: Data Types 31 Example 2-8 Using arrays with for and foreach loops initial begin bit [31:0] src[5], dst[5]; for (int i=0; i<$size(src); i++) src[i] = i; foreach (dst[j]) dst[j] = src[j] * 2; // dst doubles src values end Note that the syntax of the foreach statement for multidimensional arrays may not be what you expected! Instead of listing each subscript in sep- arate square brackets – [i][j] – they are combined with a comma – [i,j] .
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