4 Bytes Word Aligned Aligned 4 Bytes Word Misaligned Misaligned 4 Bytes Word

4 bytes word aligned aligned 4 bytes word misaligned

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4 Bytes (Word) Aligned Aligned 4 Bytes (Word) Misaligned Misaligned 4 Bytes (Word) Misaligned Misaligned 4 Bytes (Word) Misaligned Misalig. 8 bytes (Double word) Aligned 8 bytes (Double word) Misaligned 8 bytes (Double word) Misaligned 8 bytes (Double word) Misaligned 8 bytes (Double word) Misaligned 8 bytes (Double word) Misaligned 8 bytes (Double word) Misaligned 8 bytes (Double word) Misalig. FIGURE 2.5 Aligned and misaligned addresses of byte, half word, word, and double word objects for byte ad- dressed computers. For each misaligned example some objects require two memory accesses to complete. Every aligned object can always complete in one memory access, as long as the memory is as wide as the object. The figure shows the memory organized as 8 bytes wide. The byte offsets that label the columns specify the low-order three bits of the address.
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2.3 Memory Addressing 107 Even if data are aligned, supporting byte, half-word, and word accesses re- quires an alignment network to align bytes, half words, and words in 64-bit regis- ters. For example, in Figure 2.5 above, suppose we read a byte from an address with its three low order bits having the value 4. We will need shift right 3 bytes to align the byte to the proper place in a 64-bit register. Depending on the instruc- tion, the computer may also need to sign-extend the quantity. Stores are easy: only the addressed bytes in memory may be altered. On some computers a byte, half word, and word operation does not affect the upper portion of a register. Al- though all the computers discussed in this book permit byte, half-word, and word accesses to memory, only the IBM 360/370, Intel 80x86, and VAX supports ALU operations on register operands narrower than the full width. Now that we have discussed alternative interpretations of memory addresses, we can discuss the ways addresses are specified by instructions, called address- ing modes . Addressing Modes Given an address, we now know what bytes to access in memory. In this sub- section we will look at addressing modes—how architectures specify the address of an object they will access. Addressing mode specify constants and registers in addition to locations in memory. When a memory location is used, the actual memory address specified by the addressing mode is called the effective address . Figure 2.6 above shows all the data-addressing modes that have been used in recent computers. Immediates or literals are usually considered memory-address- ing modes (even though the value they access is in the instruction stream), al- though registers are often separated. We have kept addressing modes that depend on the program counter, called PC-relative addressing , separate. PC-relative ad- dressing is used primarily for specifying code addresses in control transfer instruc- tions, discussed in section 2.9.
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