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# 20 marks solution state behavior of the dma

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(20-marks) Solution: State behavior of the DMA controller: condensed state table Inputs Present Next Outputs IOREQ CONT MACK PBGNT State State PBREQ CNTLD CMREQ RLD CE 0 d d d S 0 S 0 0 0 0 0 0 1 d d d S 0 S 1 0 0 0 0 0 d d d 0 S 1 S 1 1 0 0 0 0 d d d 1 S 1 S 2 1 0 0 0 0 d d 0 d S 2 S 2 0 1 1 0 0 d d 1 d S 2 S 3 0 1 1 0 0 d d d d S 3 S 4 0 0 0 0 1 d 0 d d S 4 S 0 0 0 0 1 0 d 1 d d S 4 S 5 0 0 0 1 0 d d 0 d S 5 S 5 0 0 1 0 0 d d 1 d S 5 S 3 0 0 1 0 0

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Figure: One-hot design for the DMA controller

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22. Given flowchart for the twos’ complement multiplier control unit. Construct the state table for this controller, obtain state transition equation and output equation from your state table. Construct a typical one-hot design which all NAND gates and D filp- flop. (20-marks) ` S1 C9,C10 S3 C2,C3,C4 S2 C8 S4 C0,C1,C11 S5 C2,C3,C4,C5 S6 C6 Cycle 0 Cycle 1to 7 Cycle 8 Flowchart for twos’ complement multiplier Begin A :=0 COUNT := 0 F := 0 M := INBUS Q := INBUS Q(0):= 0? A := A + M F := M(7) AND Q(0) OR F A(0) := F A(6:0).Q := A.Q(7:1) COUNT := COUNT + 1 COUNT 7 = 1? Q(0):= 0? A := A – M Q(0) := 0 OUTBUS := Q OUTBUS := A END
Solution:

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