B Arbiter PUF With Pattern Matching Error Correction Although weak PUFs are

B arbiter puf with pattern matching error correction

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B. Arbiter PUF With Pattern Matching Error Correction Although weak PUFs are typically used for secure key generation due to their limited challenge–response space size, protocols allowing for strong PUFs to be used in this capacity have also been developed. A key challenge in adapting strong PUFs to key generation is in correcting errors in PUF response bits. To this end, Paral and Devadas have proposed the use of a ‘‘pattern matching’’ technique to correct for errors in strong PUFs for use as a key gene- ration mechanism [29]. A full description of this work is beyond the scope of this paper. In a nutshell, this approach reverses the tradi- tional challenge–response format of a PUF. In this case, a secret offset I is chosen (the key is derived from I ). A W bit portion of the response at offset I is published publicly. To recover the key, a strong PUF iterates through a deter- ministic set of challenges (which may depend on previous secret data that have been measured). The PUF response to this challenge contains the W pattern bits in the output. The PUF uses an error-tolerant comparison circuit (up to T bits of error) to identify the offset I of the W -bit block in the PUF response bits. The secret key is then derived from I . This process can be repeated several times to obtain larger sets of secret bits. The study identified that, with the correctly chosen parameters (PUF output size: 1024, W : 256, T : 80), the error occurrence could be decreased such that the PUF always succeeded in regenerating the key on the first try across environmental conditions. C. SRAM PUF Implementation As previously mentioned, the SRAM PUF leverages the threshold voltage mismatch of transistors in a SRAM cell due to manufacturing mismatch. This mismatch results in a repeatable tendency to settle into a ‘‘1’’ or ‘‘0’’ state when the SRAM cell is powered on with no writes occurring. Several studies have constructed SRAM PUFs and analyzed their properties. One of the first implementations of such a chip iden- tification system was tested by Su et al. with RFID ap- plications [37]. In this study, a custom SRAM cell was constructed to minimize potential systematic mismatch between the two transistors. Such a skew would result in a given SRAM cell being more likely to favor a ‘‘1’’ than a ‘‘0’’ or vice versa , even with random process variation. To pre- vent such systematic skew, they used analog layout tech- niques to construct a ‘‘symmetric’’ and ‘‘common centroid’’ layout of the SRAM cell. The study demonstrated that the SRAM PUF behaved as desired. After fabrication, an equal number of SRAM cells tended toward ‘‘1’’ and ‘‘0’’ to within experimental error for both layouts. The study identified that cell po- sitioning within the SRAM, SRAM positioning on the wafer, and subsequent wafers were all decorrelated with the SRAM cell’s tendency toward ‘‘1’’ or ‘‘0.’’ A challenge arose with the recognition that roughly 4%
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