Table 3 max angle error expressed in lsb of the

Table 3. Max angle error expressed in LSB of the standard vs. proposed CORDIC ( K = 12, 12 bits for x
and y data paths, six M areas).
Max. Number of Iterations
2 3 4 5 6 7 8 9 10 11 12
Standard CORDIC 512 302 252 333 374 394 404 409 412 413 414
Proposed CORDIC 512 302 160 82 43 30 40 45 48 49 50
Figure 10. Upper-bound error behavior as function of the iteration number.
4. VLSI Implementation and Characterization
The improved CORDIC architecture proposed in Section 2 has been designed in VHDL as a
parametric macrocell that can be integrated in any system-on-chip. With reference to the macrocell
configuration discussed in Section 3 , a synthesis in the standard-cell 180 nm 1.8 V CMOS technology
from AMS ag has been carried out. The macrocell design is characterized by a low circuit complexity
60

Electronics 2017 , 6 , 22
and low power consumption: about 1700 equivalent logic gates, with a max power consumption
(static and dynamic power) of about 0.45 mW when working with a clock frequency of 30 MHz.
The overhead due to the innovative parts of this work (fast magnitude estimation and input coordinates
magnification) vs. a standard CORDIC implementation in the same technology is limited to 24% in
terms of equivalent logic gates and − 36% in terms of max working frequency. The processing time of
the atan function is n
·
Tclock, i.e., 0.4 μ s when n = 12 with a clock of 30 MHz. As a possible improvement,
a pipeline register can be inserted in Figure 5 before the atan-CORDIC core. This way, the complexity
increases by about 10%, resulting in 1900 equivalent logic gates, while the working frequency can be
increased up to 46 MHz and the power consumption is 0.77 mW. The processing time is ( n + 1) · Tclock;
with n = 12 iterations of the atan function, the processing time is 0.28 μ s.
The comparison of the proposed solution vs. the standard state-of-the-art solution, implemented
in the same 180 nm 1.8 V technology, is summarized in Table 4 . Table 4 shows also the comparison with
other known CORDIC computation architectures [ 6 , 8 ]. In [ 8 ], an embedded solution is proposed using
a 32-bit ART7TDMI-S core (18,000 equivalent gates) plus 32 kB of RAM (Random Access Memory) and
512 kB of EEPROM (Electrically Erasable Programmable Read Only Memory). With a clock of 60 MHz,
the solution in [ 8 ] implements an atan evaluation in 35 μ s and an angle error of 2.42 × 10
−
5
rad with
an optimized algorithm. At 60 MHz with 180 nm 1.8 V CMOS technology, the ARM7-TDMIs has a
power consumption of about 24 mW. Although [ 8 ] is optimized to achieve a lower error, 2.42 × 10
−
5
rad vs. 6.14
×
10
3
rad in our implementation, with K = 12, the proposed design outperforms the design
in [ 8 ] in terms of the reduced processing time, by a factor × 124, the reduced power consumption, by
a factor
×
31, and the reduced circuit complexity, by a factor
×
9.5 . To achieve a similar calculation
accuracy as in [ 8 ], our IP has been re-synthetized with K = 20. In such a case, the processing time is
still within 1 μ s and the complexity in the logic gates is still below 4 kgates.