# 1531b fighting each other and producing an ill

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15.31(b)], “fighting” each other and producing an ill-defined logical output. (Also, the circuit draws significant static power from ).

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BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 806 (1) 806 Chap. 15 Digital CMOS Circuits Exercise What happens if is omitted? The above example reveals that the PMOS section must remain off if or (or both) are high. Moreover, if both inputs are low, the PMOS section must be on so as to ensure is pulled up to . Shown in Fig. 15.32(a) is such a circuit, blocking the path from to V DD M 4 (a) (b) A M 3 B out V M out V M 1 A B 2 V DD M 4 M 3 Figure 15.32 (a) PMOS section of a NOR gate, (b) complete CMOS NOR gate. if one of the inputs is high (why?), but raising to if both inputs are low. The operation, of course, remains unchanged if and are swapped. Figure 15.32(b) depicts the overall CMOS NOR implementation. The reader is encouraged to verify the operation for all four input logical combinations and prove that the circuit consumes no static power. The reader may wonder why we did not attempt to implement an OR gate. As evident from the foregoing development, the evolution of the circuit from a CMOS inverter inherently contains an inversion. If an OR gate is necessary, the topology of Fig. 15.32(b) can be followed by an inverter. Example 15.27 Construct a three-input NOR gate. Solution We expand the NMOS section of Fig. 15.30 and the PMOS section of Fig. 15.32(a) so as to accommodate three inputs. The result is depicted in Fig. 15.33. M out V M M M V DD M M 1 A B C 2 3 4 5 6 Figure 15.33
BR Wiley/Razavi/ Fundamentals of Microelectronics [Razavi.cls v. 2006] June 30, 2007 at 13:42 807 (1) Sec. 15.3 CMOS NOR and NAND Gates 807 Exercise Study the behavior of the circuit if is accidentally omitted. The principal drawback of the CMOS NOR gate stems from the use of PMOS devices in series . Recall that the low mobility of holes requires a proportionally wider PMOS transistor to obtain a symmetric VTC and, more importantly, equal rise and fall times. Viewing the transistors in a two-input NOR gate as resistors for simplicity, we observe that the PMOS section suffers from twice the resistance of each PMOS device (Example 15.23), creating a slow rising transition at the output (Fig. 15.34). If wider PMOS transistors are employed to reduce , then their gate M out V M 1 2 V DD M 4 M 3 C L R 2 on Figure 15.34 PMOS devices in series charging a load capacitance. capacitance ( ) increases, thereby loading the preceding stage. The situation worsens as the number of inputs to the gate increases. Example 15.28 Select the relative widths of the transistors in the three-input NOR gate of Fig. 15.33 for equal rise and fall times. Assume and equal channel lengths. Solution The series combination of the three PMOS devices must present a resistance equal to that of an NMOS transistor. If , then we must choose (15.98) so as to ensure that each PMOS device exhibits an on-resistance equal to one-third of that of each NMOS transistor. Note that the gate presents a capacitance of about at each input, quite larger than that of an inverter ( ).

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