Using a destination setup multicycle exception of

relationships, and blue arrows indicate hold relationships. Using a destination setup
multicycle exception of 0 also causes the default hold analysis edge to move one edge
earlier (one cycle before the launch edge).
However, hold analysis must also occur for the same launch/latch edges as the setup
analysis occurred. Adjusting the edge used for hold analysis requires a destination
hold multicycle exception with a value of –1. The value of –1 moves the latch edge
used for hold analysis one cycle later, as shown in Figure 36 . Red arrows indicate
setup relationships, and blue arrows indicate hold relationships.
Example 25.
set_multicycle_path -setup -end 0 -rise_from [get_clocks \
data_clock] -rise_to [get_clocks output_clock]
set_multicycle_path -setup -end 0 -fall_from [get_clocks \
data_clock] -fall_to [get_clocks output_clock]
set_multicycle_path -hold -end -1 -rise_from [get_clocks \
data_clock] -rise_to [get_clocks output_clock]
set_multicycle_path -hold -end -1 -fall_from [get_clocks \
data_clock] -fall_to [get_clocks output_clock]
Figure 35. Adding a Destination Multicycle Setup of Zero
Figure 36. Destination Multicycle Setup of –1
Default Setup Relationship
Default Hold Relationship
Setup Relationship with Setup Multicycle = 0
Hold Relationship with Setup Multicycle = 0
Data Clock
Output Clock
Setup Relationship with Setup Multicycle = 0
Hold Relationship with Hold Multicycle = - 1
Hold Relationship with Setup Multicycle = 0
Data Clock
Output Clock

Source-Synchronous Outputs Page 27
© May 2016 Altera Corporation AN 433: Constraining and Analyzing Source-Synchronous Interfaces
1 Using the destination multicycle exception method is not compatible with the
PrimeTime software, because the output maximum delay value is less than the output
minimum delay value.
Add One Clock Period
Figure 37 shows the default setup and hold relationships that are analyzed for
same-edge capture edge-aligned outputs. Red arrows indicate setup relationships,
and blue arrows indicate hold relationships.
Using the FPGA-centric approach to constrain the interface requires you to make
adjustments to cause the latch edge to be the same as the launch edge for setup and
hold analysis.
Figure 38 shows the setup and hold relationships that must be analyzed for SDR
same-edge capture. Red arrows indicate setup relationships, and blue arrows indicate
hold relationships.
Figure 39 shows the setup and hold relationships that must be analyzed for DDR
same-edge capture. Red arrows indicate setup relationships, and blue arrows indicate
hold relationships.
In a same-edge capture configuration, the default setup relationship is between a
rising edge and the rising edge that follows it, or a falling edge and the falling edge
that follows it. The setup relationship must be between edges that occur at the same
time. To cancel out the effect of the one-period-long setup time, you must add one
period to the output maximum delay, as shown in Equation 14 .
Figure 37. Default Setup and Hold Relationships
Figure 38. Desired Setup and Hold for SDR Same-Edge Capture
Figure 39. Desired Setup and Hold for DDR Same-Edge Capture
Data Clock
Output Clock
Data Clock
Output Clock
Data Clock
Output Clock