Chapter 6 Synthesis Optimizations 25 Architecture Reordering sum A B C D sum A

Chapter 6 synthesis optimizations 25 architecture

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Chapter 6: Synthesis & Optimizations 25 Architecture Reordering + + + sum A B C D + + + sum A B C D + + + sum A B C D sum <= A + B + C + D • Compiler parses expressions from left to right (by default) Can use parenthesis to override the default order If all input have same delay then this will optimize the speed If inputs have different delays then this will optimize the speed Chapter 6: Synthesis & Optimizations 6-49 Notes on Speed Optimization Performance Metrics Throughput (operations/second) Latency (seconds from start to finish of operation) Performance/Area/Power Exploit potential parallelism of hardware Parallel vs. Serial operation Pipelining to speed up serial operations that can not be parallelized (or don’t need parallelization) Effective memory bandwidth usually determines overall performance Search for better algorithm Search algorithms that minimize memory accesses Use shift instead of */2 , etc. Chapter 6: Synthesis & Optimizations 6-50
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EE271 @ Thuy T. Le SJSU-EE Chapter 6: Synthesis & Optimizations 26 Specify don’t cares on outputs whenever possible Does increase potential for mismatch between behavioral simulation and post-synthesis simulation. Specify multiplexers if possible Use parentheses to group items only if having special design knowledge. Example: inputs c and d arrive after a and b : output = (((a + b) + c) + d); Find parallelism whenever possible Be aware that most of synthesis tools can optimize smaller designs easier than larger ones Keep the critical path in one module It is difficult to optimize across modules Try to keep this module as small as possible Chapter 6: Synthesis & Optimizations 6-51 Setting constraints correctly is very important . Examples of constraints setting in Synopsys: set_input_delay set_output_delay set_driving_cell set_load create_clock Initially, the first four are estimated. Later those estimates can be refined once the actual fan out, wire loading, etc. is known Other constraints might have to be set, depending on library Use worst case library for set-up timing and best case for hold timing Use set_false_path on inputs that never change (e.g. configuration pins) and outputs that are asynchronous Chapter 6: Synthesis & Optimizations 6-52
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