EEE6323S13-HW3

# From the datasheets find the average intrinsic delay

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nand gate; NANDX2 has twice the drive and so forth. From the datasheets, find the average intrinsic delay of the inverter INVX1. What is the propagation delay t pd of an inverter driving a fanout of h gates? Determine the parasitic delay p (HINT: determine τ from the slope of delay vs. fanout as explained in class) 10 x x y z 100 A B z 200 C y

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Problem 4 – Buffer Sizing The circuit below is a latch with buffered clock input CK grid . Assume Lp=Ln=Lmin and the transistor widths WN1=WN4=10xWmin and WN2=WN3=Wmin, where Wmin=0.36um and Lmin=0.25um. Assume node Q drives 4 minimum sized inverters, or FO4 (the inverters should be sized such that β n/ β p ~ 1). Use parameters from Table 5.5 (Weste and Harris) for hand calculations. (1) Given the transistor sizes for the nMOS transistors in the latch, determine the size of P1, P2, P3 and P4. Recall that the TGATE and P4/N4 inverter constitutes the signal path and the feedback transistor (P2-P3 and N2-N3) is the storage inverter. (2) Determine the minimum size (i.e. transistor widths) of INV1 and INV2 such that the rise/fall times at nodes CK and CKb are within 100ps. Size the inverters for symmetric VTC. Use hand calculations.
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• Spring '10
• bashir
• Transistor, Logic gate, worst case delay, hand calculations, propagation delay tpd, average intrinsic delay

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