Design Compiler optimization uses net fanout as a basis for estimating interconnect wire length from the wire load model. Design Compiler uses this information to calculate interconnect wiring and transition delays. The wire load model for a design depends on the estimated die size of the design. Wire load models are defined in the target library. Design Compiler uses area as a basis for automatically selecting the wire load tables if your ASIC libraries support this feature. To set the wire load, choose Attributes > Operating Environment > Wire Loadand the Wire Loadwindow will be opened with the listing of the wire load models and the target library. For this tutorial, let's use 10x10 class, which corresponds to a die size of 1mm x 1mm. Click O.K.to select the wire load model and then click Cancelto close the window.
Figure 12: Wire Loadwindow The operating conditions of the design are the temperature, process, and voltage in which the design operates. The target library defines the operating conditions. Library vendors define default operating conditions, which can differ from one vendor to another. The Design Compiler static timing analyzer models the effects of variation in the drive strength, arrival time, and load values on a circuit’s timing characteristics. In a similar way, you can analyze a design for best-case, nominal-case, and worst-case performance or operating conditions. The setting of the operating conditions can be done by command Attributes | Operating Environment | Operating Conditions. For this tutorial, select the operating conditions as shown in Figure 13, where each set of operating conditions is followed by the name of the target library in parentheses. Figure 13: Operating Conditionswindow You should now save your design to preserve your attribute settings. To save the design in .dbformat, choose File | Save Asto open the Save Designwindow. Navigate to the db/directory in the Directorymenu and name your design as counter_att.db(remember to choose DBas the File Format). When a design is
saved as a .dbfile, the design and all attributes are saved. Make sure that the Save All Designs in Hierarchyoption is set to on. Figure 14: Save Filewindow You also can check for missing files by selecting Analysis | Link Designfrom the main window. The link command checks to make sure all parts in the current design are available in Design_Analyzer's memory. If there is a missing part (also known as unresolved reference), the information will be saved in a .dbfile and this file is read in automatically during the execution of the link command. After selecting the Analysis | Link Design, the Link Designwindow will pop up as shown in Figure 15. Clicking OKwill start the link process and a Link Reportwindow will pop up. After examine the link result, cancel the Link Reportwindow. Figure 15: Link Designwindow
To check your design's netlist description for problems like connectivity, shorts, opens, multiple instantiations, select Analysis | Check Design. You can also check for potential timing problems (i.e. no clocks specified, outputs unconstrained for time) by clicking on Check Timing. You may also select Analysis | Report | Portand click on