Instruction Set Architectures ISAs Instruction Set Architectures ISAs CISC 2

Instruction set architectures isas instruction set

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Instruction Set Architectures (ISAs) Instruction Set Architectures (ISAs) CISC: (2 movs x 1 cycle) + (1 mul x 30 cycles) = 32 cycles RISC: (3 movs x 1 cycle) + (5 adds x 1cycle) + (5 loops x 1 cycle) = 13 cycle Micro-architecture Implementations: Simple instruction set of RISC machines takes less time to interpret plus less hardware Enables control unit to be hardwired for max. speed Also allows room for performance enhancement such as pipelining Fewer instructions would mean fewer transistors, in turn less manufacturing cost More complex & variable instruction set of CISC machines require more translation takes time as well more hardware Usually implemented as microprogrammed control to tackle variable length instructions Due to load-store ISAs, RISC architectures require large number of registers These register provide fast access to data during sequential program execution 40 CISC Mov ax, 10 Mov bx, 5 Mul bx, ax RISC Mov ax, 0 Mov bx, 10 Mov cx, 5 Begin Add ax, bx Loop begin
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21 Intel Architecture, 32-bits (IA-32) IA-32 often called i386, x86-32 or even x86, is the instruction set architecture of Intel's most commercially successful uP. It is a 32-bit extension of x86, first implemented in Intel 80386, of earlier 16-bit Intel 8086, 80186 & 80286 processors & common denominator for all subsequent x86 designs This architecture defines instruction set for family of uPs installed in vast majority of personal computers in the world IA-32 instruction set is usually described as CISC architecture 41 RISC Simple instructions, few in number Fixed length instructions Complexity in compiler Only Load/Store instructions access memory Few addressing modes uC with Harvard architecture are also called RISC uC Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" & "STORE“ are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers CISC Many complex instructions Variable length instructions Complexity in microcode Many instructions can access memory Many addressing modes uC with von-Neumann's architecture are called CISC uC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" & "STORE“ incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions 42 RISC Vs CISC
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22 8051 Instruction set The instruction set is divided in to 5 categories: 1. Arithmetic instructions 2. Logic instructions 3. Data transfer instructions 4. Boolean variable manipulation instruction 5. Program & machine control instruction 43 Arithmetic Instructions 44
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23 Logic Instructions 45 Data Transfer Instructions 46
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24 Boolean Variable Manipulation Instructions 47 Program & Machine Control Instructions 48
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