291 Aborted Faults 292 Addressing Aborted Faults 293 Addressing Aborted Faults

291 aborted faults 292 addressing aborted faults 293

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291 Aborted Faults .................................................................................................................................. 292 Addressing Aborted Faults ............................................................................................................... 293 Addressing Aborted Faults (Cont.) .................................................................................................. 294 Fault-by-Fault UC Debugging: report_faults Command ................................................................. 295
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Table of Contents Tessent Scan and ATPG XII Fault-by-Fault UC Debugging: analyze_fault Command ................................................................ 296 Fault-by-Fault UC Debugging: report_test_stimulus Command ..................................................... 297 Faults Class: ATPG Untestable ........................................................................................................ 298 Tools for Debugging AU Faults: set_gate_report Command .......................................................... 299 Constrain State Reporting ................................................................................................................ 300 Tools for Debugging AU Faults: Stuck-at Faults ............................................................................. 301 Tools for Debugging AU Faults: Transition Faults ......................................................................... 302 Debugging Transition/Path Delay Faults: Cell Constraints Can Prevent Detection ....................... 303 Debugging Transition/Path Delay Faults: Perform a Stuck-at Test for Sites Along Path .............. 304 Adding Primary Input Points For Investigation ............................................................................... 305 ATPG Event Simulation ................................................................................................................... 306 Event Simulation: DFFs and Latches ............................................................................................... 307 Example 1: Reporting Pattern Index ................................................................................................ 308 Example 2: Reporting Parallel Pattern 0 .......................................................................................... 309 Example 3: DRC Pattern Load_Unload ........................................................................................... 310 Lab 7: Troubleshooting Low Coverage ........................................................................................... 311 Module 8: Simulation Mismatch ........................................................................ 313 Objectives ......................................................................................................................................... 314 Verilog Testbenches ......................................................................................................................... 315 Parameter Options for the Verilog Testbench .................................................................................. 316 Controlling Messaging ..................................................................................................................... 317 SIM_VECTYPE_SIGNAL .............................................................................................................. 318 Serial Testbench ............................................................................................................................... 319 Serial Pattern Verification ................................................................................................................ 320 Parallel Verilog Testbench ............................................................................................................... 321
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Table of Contents Tessent Scan and ATPG XIII Testbenches: Recommended Simulation Order ............................................................................... 322 Simulation Mismatches: Steps ......................................................................................................... 323 Required Debug Files ....................................................................................................................... 324 Mismatch Report .............................................................................................................................. 325 Shift or Capture Problem? ................................................................................................................ 326 Shift or Capture Problem? (Cont.) ................................................................................................... 327 Parallel Testbench Mismatch ........................................................................................................... 328 Parallel Testbench Trace Back ......................................................................................................... 329 Parallel Testbench Trace Back (Cont.) ............................................................................................ 330 Parallel Testbench Trace Back (Cont.) ............................................................................................ 331 Parallel Testbench Trace Back (Cont.) ............................................................................................ 332 Typical Distribution of Problem Types ............................................................................................ 333 Possible Mismatch Causes: Clock Skew Problems .......................................................................... 334 Possible Mismatch Causes: Clock Skew Problems(Cont.) .............................................................. 335 Possible Mismatch Causes: Timing Violations ................................................................................ 336 Possible Mismatch Causes: DRC Violations ................................................................................... 337 Possible Mismatch Causes: Library Problems ................................................................................. 338 Modeling Abstraction ....................................................................................................................... 339 Library Verification Flow ................................................................................................................ 340 Library Verification With LibComp ................................................................................................ 341 Possible Mismatch Causes: Modeling Issues ................................................................................... 342 Possible Mismatch Causes: Mux Model Pessimism ........................................................................ 343 Possible Mismatch Causes: ATPG Switch Models .......................................................................... 344 Possible Mismatch Causes: ROM / RAM Initialization Data .......................................................... 345 Possible Mismatch Causes: Weak Pulls ........................................................................................... 346
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Table of Contents Tessent Scan and ATPG XIV Possible Mismatch Causes: Black Boxes ......................................................................................... 347 Possible Mismatch Causes: Simulation Settings .............................................................................. 348 X Clock Handling ............................................................................................................................. 349 Bus Simulation ................................................................................................................................. 350 Set Z Handling ................................................................................................................................. 351 Possible Mismatch Causes: Internal Primary Inputs ........................................................................ 352 Pattern Masking ................................................................................................................................ 353 Pattern Masking (Cont.) ................................................................................................................... 354 Automatic Simulation Mismatch Analysis Flow ............................................................................. 355 Analyze Simulation Mismatches ...................................................................................................... 356 ModelSim Invocation Script ............................................................................................................ 357 Report Mismatch Sources Command ............................................................................................... 358 Lab 8: Debug Simulation Mismatches ............................................................................................. 359 Module 9: Compression ...................................................................................... 361 Objectives ......................................................................................................................................... 362 Understanding the ATPG Process .................................................................................................... 363 Standard Test Application Process ................................................................................................... 364 ATPG-Based Compression Techniques ........................................................................................... 365 Static Compression ........................................................................................................................... 366 Dynamic Compression ..................................................................................................................... 367 Clock Domain Analysis and Clock Merging ................................................................................... 368 Multiple Clock Capture per Pattern ................................................................................................. 369 ATPG Create Patterns Command .................................................................................................... 370 ATPG Create Patterns Command (Cont.) ........................................................................................ 371 Balanced Scan Chains ...................................................................................................................... 372
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Table of Contents Tessent Scan and ATPG XV
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