GPCMUX2 1 0 or 1 1 no qual 16 1 0 GPIO80 IO XA8 O 17 3 2 GPIO81 IO XA9 O 18 5 4

Gpcmux2 1 0 or 1 1 no qual 16 1 0 gpio80 io xa8 o 17

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GPCMUX2 = 1, 0 or 1, 1 no qual 16 1, 0 GPIO80 (I/O) XA8 (O) 17 3, 2 GPIO81 (I/O) XA9 (O) 18 5, 4 GPIO82 (I/O) XA10 (O) 19 7, 6 GPIO83 (I/O) XA11 (O) 20 9, 8 GPIO84 (I/O) XA12 (O) 21 11, 10 GPIO85 (I/O) XA13 (O) 22 13, 12 GPIO86 (I/O) XA14 (O) 23 15, 14 GPIO87 (I/O) XA15 (O) Copyright © 2007–2010, Texas Instruments Incorporated Peripherals 105 Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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GPyCTRL Reg SYNC SYSCLKOUT Qualification Input Signal Qualified by 3 or 6 Samples GPIOx Time Between Samples GPxQSEL Number of Samples TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT). Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change. Figure 4-19. Qualification Using Sampling Window The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-19 (for 6-sample mode). No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral). Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral. 106 Peripherals Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F28335 TMS320F28334 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232
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XD[31:0] XA[19:0] XZCS0 XZCS6 XZCS7 XINTF Zone 0 (8K x 16) 0x0030-0000 0x0020-0000 0x0010-0000 0x0000-5000 0x0000-4000 0x0000-0000 Data Space Prog Space XINTF Zone 6 (1M x 16) XWE0 XR/W XREADY XHOLD XHOLDA XCLKOUT XRD XA0/XWE1 XINTF Zone 7 (1M x 16) TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439H–JUNE 2007–REVISED MARCH 2010 4.14 External Interface (XINTF) This section gives a top-level view of the external interface (XINTF) that is implemented on the 2833x/2823x devices. The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three fixed zones shown in Figure 4-20 . A. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip selects that toggle when an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals.
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